Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 5 | * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <delay.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <device/pci_ops.h> |
| 23 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 24 | #include <device/mmio.h> |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 25 | #include <option.h> |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 26 | #include "sb700.h" |
| 27 | |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 28 | static int sata_drive_detect(int portnum, uint16_t iobar) |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 29 | { |
| 30 | u8 byte, byte2; |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 31 | u8 byte_prev, byte2_prev; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 32 | int i = 0; |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 33 | byte_prev = byte2_prev = 0; |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 34 | outb(0xa0 + 0x10 * (portnum % 2), iobar + 0x6); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 35 | while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 36 | (byte != (0xa0 + 0x10 * (portnum % 2))) || |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 37 | ((byte2 & 0x88) != 0)) { |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 38 | if ((byte != byte_prev) || (byte2 != byte2_prev)) |
| 39 | printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 40 | if (byte != (0xa0 + 0x10 * (portnum % 2))) { |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 41 | /* This will happen at the first iteration of this loop |
| 42 | * if the first SATA port is unpopulated and the |
Martin Roth | dcf253c | 2014-12-16 20:51:31 -0700 | [diff] [blame] | 43 | * second SATA port is populated. |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 44 | */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 45 | printk(BIOS_DEBUG, "drive no longer selected after %i ms, " |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 46 | "retrying init\n", i * 10); |
| 47 | return 1; |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 48 | } else { |
| 49 | if (i == 0) |
| 50 | printk(BIOS_SPEW, "drive detection not yet completed, " |
| 51 | "waiting...\n"); |
| 52 | } |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 53 | mdelay(10); |
| 54 | i++; |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 55 | byte_prev = byte; |
| 56 | byte2_prev = byte2; |
| 57 | |
| 58 | /* Detect stuck SATA controller and attempt reset */ |
| 59 | if (i > 1024) { |
| 60 | printk(BIOS_DEBUG, "drive detection not done after %i ms, " |
| 61 | "resetting HBA and retrying init\n", i * 10); |
| 62 | return 2; |
| 63 | } |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 64 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 65 | printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 66 | return 0; |
| 67 | } |
| 68 | |
Zheng Bao | a5c949e | 2011-01-27 03:31:50 +0000 | [diff] [blame] | 69 | /* This function can be overloaded in mainboard.c */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 70 | void __weak sb7xx_51xx_setup_sata_phys(struct device *dev) |
Zheng Bao | a5c949e | 2011-01-27 03:31:50 +0000 | [diff] [blame] | 71 | { |
Rudolf Marek | 7df50a8 | 2010-09-22 22:46:47 +0000 | [diff] [blame] | 72 | /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ |
| 73 | pci_write_config16(dev, 0x86, 0x2c00); |
| 74 | |
| 75 | /* RPR7.6.2 SATA GENI PHY ports setting */ |
| 76 | pci_write_config32(dev, 0x88, 0x01B48017); |
| 77 | pci_write_config32(dev, 0x8c, 0x01B48019); |
| 78 | pci_write_config32(dev, 0x90, 0x01B48016); |
| 79 | pci_write_config32(dev, 0x94, 0x01B48016); |
| 80 | pci_write_config32(dev, 0x98, 0x01B48016); |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 81 | pci_write_config32(dev, 0x9c, 0x01B48016); |
Rudolf Marek | 7df50a8 | 2010-09-22 22:46:47 +0000 | [diff] [blame] | 82 | |
| 83 | /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */ |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 84 | pci_write_config16(dev, 0xa0, 0xA09A); |
| 85 | pci_write_config16(dev, 0xa2, 0xA09F); |
| 86 | pci_write_config16(dev, 0xa4, 0xA07A); |
| 87 | pci_write_config16(dev, 0xa6, 0xA07A); |
| 88 | pci_write_config16(dev, 0xa8, 0xA07A); |
| 89 | pci_write_config16(dev, 0xaa, 0xA07A); |
Rudolf Marek | 7df50a8 | 2010-09-22 22:46:47 +0000 | [diff] [blame] | 90 | } |
| 91 | |
Timothy Pearson | f89a05e | 2015-06-09 19:34:16 -0500 | [diff] [blame] | 92 | /* This function can be overloaded in mainboard.c */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 93 | void __weak sb7xx_51xx_setup_sata_port_indication(void *sata_bar5) |
Timothy Pearson | f89a05e | 2015-06-09 19:34:16 -0500 | [diff] [blame] | 94 | { |
| 95 | uint32_t dword; |
| 96 | |
| 97 | /* RPR7.9 Program Port Indication Registers */ |
| 98 | dword = read32(sata_bar5 + 0xf8); |
| 99 | dword &= ~(0x3f << 12); /* Ports 0 and 1 are eSATA */ |
| 100 | dword |= (0x3 << 12); |
| 101 | dword &= ~0x3f; |
| 102 | write32(sata_bar5 + 0xf8, dword); |
| 103 | |
| 104 | dword = read32(sata_bar5 + 0xfc); |
| 105 | dword |= 0x1 << 20; /* At least one eSATA port is present */ |
| 106 | write32(sata_bar5 + 0xfc, dword); |
| 107 | } |
| 108 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 109 | static void sata_init(struct device *dev) |
| 110 | { |
| 111 | u8 byte; |
| 112 | u16 word; |
| 113 | u32 dword; |
| 114 | u8 rev_id; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 115 | void *sata_bar5; |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 116 | uint16_t sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; |
| 117 | uint16_t ide_bar0, ide_bar1, ide_bar2, ide_bar3; |
| 118 | uint16_t current_bar; |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 119 | int i, j, ret; |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 120 | uint8_t nvram; |
| 121 | uint8_t sata_ahci_mode; |
Timothy Pearson | 83b7761 | 2015-06-18 11:48:02 -0500 | [diff] [blame] | 122 | uint8_t sata_alpm_enable; |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 123 | uint8_t port_count; |
| 124 | uint8_t max_port_count; |
Timothy Pearson | 0111459 | 2015-06-22 02:56:10 -0500 | [diff] [blame] | 125 | uint8_t ide_io_enabled; |
| 126 | uint8_t ide_legacy_io_enabled; |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 127 | |
| 128 | sata_ahci_mode = 0; |
| 129 | if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) |
| 130 | sata_ahci_mode = !!nvram; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 131 | |
Timothy Pearson | 83b7761 | 2015-06-18 11:48:02 -0500 | [diff] [blame] | 132 | sata_alpm_enable = 0; |
| 133 | if (get_option(&nvram, "sata_alpm") == CB_SUCCESS) |
| 134 | sata_alpm_enable = !!nvram; |
| 135 | |
Elyes HAOUAS | f29a689 | 2018-05-19 12:37:54 +0200 | [diff] [blame] | 136 | struct device *sm_dev; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 137 | /* SATA SMBus Disable */ |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 138 | sm_dev = pcidev_on_root(0x14, 0); |
Wang Qing Pei | 16d3ec6 | 2010-11-09 09:17:07 +0100 | [diff] [blame] | 139 | |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 140 | /* WARNING |
| 141 | * Enabling the SATA link latency enhancement (SMBUS 0xAD bit 5) |
| 142 | * causes random persistent drive detection failures until it is cleared, |
| 143 | * with the probabability of detection failure rising exponentially with |
| 144 | * the number of drives attached to the controller! |
| 145 | * This happens on Rev15 H/W. |
| 146 | * Do NOT follow the RPR advice; leave this bit set at all times... |
| 147 | */ |
Wang Qing Pei | 16d3ec6 | 2010-11-09 09:17:07 +0100 | [diff] [blame] | 148 | byte = pci_read_config8(sm_dev, 0xad); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 149 | /* Disable SATA SMBUS */ |
Wang Qing Pei | 16d3ec6 | 2010-11-09 09:17:07 +0100 | [diff] [blame] | 150 | byte |= (1 << 1); |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 151 | /* Enable SATA and power saving */ |
| 152 | byte |= (1 << 0); |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 153 | /* Disable link latency enhancement */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 154 | byte |= (1 << 5); |
| 155 | pci_write_config8(sm_dev, 0xad, byte); |
| 156 | |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 157 | /* Take the PHY logic out of reset */ |
| 158 | word = pci_read_config16(dev, 0x84); |
| 159 | word |= 0x1 << 2; |
| 160 | word &= ~0x1f8; |
| 161 | pci_write_config16(dev, 0x84, word); |
| 162 | |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 163 | /* get rev_id */ |
| 164 | rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; |
| 165 | |
Timothy Pearson | 14ebf95 | 2015-06-21 16:27:03 -0500 | [diff] [blame] | 166 | printk(BIOS_SPEW, "rev_id=%x\n", rev_id); |
| 167 | |
Timothy Pearson | 0111459 | 2015-06-22 02:56:10 -0500 | [diff] [blame] | 168 | /* Enable combined mode */ |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 169 | byte = pci_read_config8(sm_dev, 0xad); |
Timothy Pearson | 0111459 | 2015-06-22 02:56:10 -0500 | [diff] [blame] | 170 | byte |= (1 << 3); |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 171 | pci_write_config8(sm_dev, 0xad, byte); |
| 172 | |
Elyes HAOUAS | f29a689 | 2018-05-19 12:37:54 +0200 | [diff] [blame] | 173 | struct device *ide_dev; |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 174 | /* IDE Device */ |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 175 | ide_dev = pcidev_on_root(0x14, 1); |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 176 | |
Timothy Pearson | 0111459 | 2015-06-22 02:56:10 -0500 | [diff] [blame] | 177 | /* Disable legacy IDE mode (enable PATA_BAR0/2) */ |
| 178 | byte = pci_read_config8(ide_dev, 0x09); |
| 179 | ide_legacy_io_enabled = !(byte & 0x1); |
| 180 | byte |= 0x1; |
| 181 | pci_write_config8(ide_dev, 0x09, byte); |
| 182 | |
| 183 | /* Enable IDE I/O access (enable PATA_BAR0/2) */ |
| 184 | byte = pci_read_config8(ide_dev, 0x04); |
| 185 | ide_io_enabled = byte & 0x1; |
| 186 | byte |= 0x1; |
| 187 | pci_write_config8(ide_dev, 0x04, byte); |
| 188 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 189 | /* RPR 7.2 SATA Initialization */ |
| 190 | /* Set the interrupt Mapping to INTG# */ |
| 191 | byte = pci_read_config8(sm_dev, 0xaf); |
| 192 | byte = 0x6 << 2; |
| 193 | pci_write_config8(sm_dev, 0xaf, byte); |
| 194 | |
Zheng Bao | 2a5101a | 2010-10-10 15:18:53 +0000 | [diff] [blame] | 195 | /* get base address */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 196 | sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 197 | sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; |
| 198 | sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; |
| 199 | sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7; |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 200 | sata_bar3 = pci_read_config16(dev, 0x1c) & ~0x3; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 201 | sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; |
| 202 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 203 | printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ |
| 204 | printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */ |
| 205 | printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ |
| 206 | printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ |
| 207 | printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 208 | printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 209 | |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 210 | ide_bar0 = pci_read_config16(ide_dev, 0x10) & ~0x7; |
| 211 | ide_bar1 = pci_read_config16(ide_dev, 0x14) & ~0x3; |
| 212 | ide_bar2 = pci_read_config16(ide_dev, 0x18) & ~0x7; |
| 213 | ide_bar3 = pci_read_config16(ide_dev, 0x1c) & ~0x3; |
| 214 | printk(BIOS_SPEW, "ide_bar0=%x\n", ide_bar0); |
| 215 | printk(BIOS_SPEW, "ide_bar1=%x\n", ide_bar1); |
| 216 | printk(BIOS_SPEW, "ide_bar2=%x\n", ide_bar2); |
| 217 | printk(BIOS_SPEW, "ide_bar3=%x\n", ide_bar3); |
| 218 | |
| 219 | /* Program the Subsystem ID/VID to 0x43801002 */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 220 | dword = 0x43801002; |
| 221 | pci_write_config32(dev, 0x2c, dword); |
| 222 | |
| 223 | /* SERR-Enable */ |
| 224 | word = pci_read_config16(dev, 0x04); |
| 225 | word |= (1 << 8); |
| 226 | pci_write_config16(dev, 0x04, word); |
| 227 | |
| 228 | /* Dynamic power saving */ |
| 229 | byte = pci_read_config8(dev, 0x40); |
| 230 | byte |= (1 << 2); |
| 231 | pci_write_config8(dev, 0x40, byte); |
| 232 | |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 233 | /* Unlock subclass and certain BAR R/O registers */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 234 | byte = pci_read_config8(dev, 0x40); |
| 235 | byte |= (1 << 0); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 236 | pci_write_config8(dev, 0x40, byte); |
| 237 | |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 238 | /* Disable AHCI enhancement (AMD SP5100 RPR page 54) */ |
| 239 | dword = pci_read_config32(dev, 0x40); |
| 240 | dword |= (1 << 23); |
| 241 | pci_write_config32(dev, 0x40, dword); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 242 | |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 243 | if (sata_ahci_mode) { |
| 244 | /* Force number of ports to 6 |
| 245 | * NOTE: This is not documented in the register |
| 246 | * reference guide, but CIMX needs to do this |
| 247 | * to activate all 6 ports when IDE is disabled. |
| 248 | */ |
| 249 | dword = read32(sata_bar5 + 0x00); |
| 250 | dword &= ~0x7; |
| 251 | dword |= 0x5; |
| 252 | write32(sata_bar5 + 0x00, dword); |
| 253 | } else { |
| 254 | /* Set SATA Operation Mode, Set to IDE mode */ |
| 255 | byte = pci_read_config8(dev, 0x40); |
| 256 | byte |= (1 << 4); |
| 257 | pci_write_config8(dev, 0x40, byte); |
| 258 | |
| 259 | dword = 0x01018f00; |
| 260 | pci_write_config32(dev, 0x8, dword); |
| 261 | } |
| 262 | |
| 263 | /* Get maximum number of ports */ |
| 264 | max_port_count = read32(sata_bar5 + 0x00) & 0x1f; |
| 265 | max_port_count++; |
| 266 | printk(BIOS_SPEW, "Maximum SATA port count supported by silicon: %d\n", max_port_count); |
| 267 | |
| 268 | /* Set number of ports */ |
| 269 | dword = CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD; |
| 270 | for (i = max_port_count; i < 32; i++) |
| 271 | dword &= ~(0x1 << i); |
| 272 | write32(sata_bar5 + 0x0c, dword); |
| 273 | |
Timothy Pearson | 83b7761 | 2015-06-18 11:48:02 -0500 | [diff] [blame] | 274 | /* Disable ALPM if ALPM support not requested */ |
| 275 | if (!sata_alpm_enable) { |
| 276 | dword = read32(sata_bar5 + 0xfc); |
| 277 | dword &= ~(0x1 << 11); /* Disable ALPM */ |
| 278 | write32(sata_bar5 + 0xfc, dword); |
| 279 | } |
| 280 | |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 281 | /* Enable SATA ports */ |
| 282 | byte = pci_read_config8(dev, 0x42); |
| 283 | if (max_port_count <= 6) { |
| 284 | byte |= 0x3f; |
| 285 | for (i = 0; i < max_port_count; i++) |
| 286 | byte &= ~(0x1 << i); |
| 287 | } else { |
| 288 | byte &= ~0x3f; |
| 289 | } |
| 290 | pci_write_config8(dev, 0x42, byte); |
| 291 | |
Timothy Pearson | 14ebf95 | 2015-06-21 16:27:03 -0500 | [diff] [blame] | 292 | if (sata_ahci_mode) { |
| 293 | /* FIXME |
| 294 | * SeaBIOS does not know how to spin |
| 295 | * up the drives and therefore hangs |
| 296 | * in AHCI init if this is enabled... |
| 297 | */ |
| 298 | /* Enable staggered spin-up */ |
| 299 | dword = read32(sata_bar5 + 0x00); |
| 300 | #if 0 |
| 301 | dword |= 0x1 << 27; |
| 302 | #else |
| 303 | dword &= ~(0x1 << 27); |
| 304 | #endif |
| 305 | write32(sata_bar5 + 0x00, dword); |
| 306 | |
| 307 | /* Reset the HBA to avoid stuck drives in SeaBIOS */ |
| 308 | dword = read32(sata_bar5 + 0x04); |
| 309 | dword |= 0x1; |
| 310 | write32(sata_bar5 + 0x04, dword); |
| 311 | } |
| 312 | |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 313 | sb7xx_51xx_setup_sata_phys(dev); |
| 314 | sb7xx_51xx_setup_sata_port_indication(sata_bar5); |
| 315 | |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 316 | /* Write protect Sub-Class Code */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 317 | byte = pci_read_config8(dev, 0x40); |
| 318 | byte &= ~(1 << 0); |
| 319 | pci_write_config8(dev, 0x40, byte); |
| 320 | |
| 321 | /* Enable the SATA watchdog counter */ |
| 322 | byte = pci_read_config8(dev, 0x44); |
| 323 | byte |= (1 << 0); |
| 324 | pci_write_config8(dev, 0x44, byte); |
| 325 | |
| 326 | /* Set bit 29 and 24 for A12 */ |
| 327 | dword = pci_read_config32(dev, 0x40); |
| 328 | if (rev_id < 0x14) /* before A12 */ |
| 329 | dword |= (1 << 29); |
| 330 | else |
| 331 | dword &= ~(1 << 29); /* A14 and above */ |
| 332 | pci_write_config32(dev, 0x40, dword); |
| 333 | |
| 334 | /* set bit 21 for A12 */ |
| 335 | dword = pci_read_config32(dev, 0x48); |
| 336 | if (rev_id < 0x14) /* before A12 */ |
| 337 | dword |= 1 << 24 | 1 << 21; |
| 338 | else { |
| 339 | dword &= ~(1 << 24 | 1 << 21); /* A14 and above */ |
| 340 | dword &= ~0xFF80; /* 15:7 */ |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 341 | dword |= 1 << 15 | 0x7F << 7 | 1 << 6; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 342 | } |
| 343 | pci_write_config32(dev, 0x48, dword); |
| 344 | |
| 345 | /* Program the watchdog counter to 0x10 */ |
| 346 | byte = 0x10; |
| 347 | pci_write_config8(dev, 0x46, byte); |
Timothy Pearson | f89a05e | 2015-06-09 19:34:16 -0500 | [diff] [blame] | 348 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 349 | /* Enable the I/O, MM, BusMaster access for SATA */ |
| 350 | byte = pci_read_config8(dev, 0x4); |
| 351 | byte |= 7 << 0; |
| 352 | pci_write_config8(dev, 0x4, byte); |
| 353 | |
Martin Roth | 083504b | 2017-06-24 21:30:14 -0600 | [diff] [blame] | 354 | #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100) |
Zheng Bao | c342223 | 2011-03-28 03:33:10 +0000 | [diff] [blame] | 355 | /* Master Latency Timer */ |
| 356 | pci_write_config32(dev, 0xC, 0x00004000); |
| 357 | #endif |
| 358 | |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 359 | /* Determine port count */ |
| 360 | port_count = 0; |
| 361 | for (i = 0; i < 32; i++) { |
| 362 | if (CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD & (0x1 << i)) |
| 363 | port_count = i; |
| 364 | } |
| 365 | port_count++; |
| 366 | if (port_count > max_port_count) |
| 367 | port_count = max_port_count; |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 368 | |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 369 | /* Send COMRESET to all ports */ |
| 370 | for (i = 0; i < port_count; i++) { |
| 371 | /* Read in Port-N Serial ATA Control Register */ |
| 372 | byte = read8(sata_bar5 + 0x12C + 0x80 * i); |
| 373 | |
| 374 | /* Set Reset Bit */ |
| 375 | byte |= 0x1; |
| 376 | write8((sata_bar5 + 0x12C + 0x80 * i), byte); |
| 377 | |
| 378 | /* Wait 1ms */ |
| 379 | mdelay(1); |
| 380 | |
| 381 | /* Clear Reset Bit */ |
| 382 | byte &= ~0x01; |
| 383 | write8((sata_bar5 + 0x12C + 0x80 * i), byte); |
| 384 | |
| 385 | /* Wait 1ms */ |
| 386 | mdelay(1); |
| 387 | } |
| 388 | |
Timothy Pearson | 398540f | 2015-06-20 21:31:15 -0500 | [diff] [blame] | 389 | /* RPR7.7 SATA drive detection. */ |
| 390 | /* Use BAR5+0x128,BAR0 for Primary Slave */ |
| 391 | /* Use BAR5+0x1A8,BAR0 for Primary Slave */ |
| 392 | /* Use BAR5+0x228,BAR2 for Secondary Master */ |
| 393 | /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ |
| 394 | /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */ |
| 395 | /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ |
| 396 | for (i = 0; i < port_count; i++) { |
| 397 | byte = read8(sata_bar5 + 0x128 + 0x80 * i); |
| 398 | printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); |
| 399 | byte &= 0xF; |
| 400 | if (byte == 0x1) { |
| 401 | /* If the drive status is 0x1 then we see it but we aren't talking to it. */ |
| 402 | /* Try to do something about it. */ |
| 403 | printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); |
| 404 | |
| 405 | /* Read in Port-N Serial ATA Control Register */ |
| 406 | byte = read8(sata_bar5 + 0x12C + 0x80 * i); |
| 407 | |
| 408 | /* Set Reset Bit and 1.5g bit */ |
| 409 | byte |= 0x11; |
| 410 | write8((sata_bar5 + 0x12C + 0x80 * i), byte); |
| 411 | |
| 412 | /* Wait 1ms */ |
| 413 | mdelay(1); |
| 414 | |
| 415 | /* Clear Reset Bit */ |
| 416 | byte &= ~0x01; |
| 417 | write8((sata_bar5 + 0x12C + 0x80 * i), byte); |
| 418 | |
| 419 | /* Wait 1ms */ |
| 420 | mdelay(1); |
| 421 | |
| 422 | /* Reread status */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 423 | byte = read8(sata_bar5 + 0x128 + 0x80 * i); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 424 | printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 425 | byte &= 0xF; |
Timothy Pearson | 398540f | 2015-06-20 21:31:15 -0500 | [diff] [blame] | 426 | } |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 427 | |
Timothy Pearson | 398540f | 2015-06-20 21:31:15 -0500 | [diff] [blame] | 428 | if (byte == 0x3) { |
| 429 | for (j = 0; j < 10; j++) { |
| 430 | if (i < 4) |
| 431 | current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; |
| 432 | else |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 433 | current_bar = (pci_read_config8(sm_dev, 0xad) & (0x1 << 4)) |
| 434 | ? ide_bar2 : ide_bar0; |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 435 | ret = sata_drive_detect(i, current_bar); |
| 436 | if (ret == 0) { |
Timothy Pearson | 398540f | 2015-06-20 21:31:15 -0500 | [diff] [blame] | 437 | break; |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 438 | } else if (ret == 2) { |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 439 | /* Read in Port-N Serial ATA Control Register */ |
| 440 | byte = read8(sata_bar5 + 0x12C + 0x80 * i); |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 441 | |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 442 | /* Set Reset Bit */ |
| 443 | byte |= 0x1; |
| 444 | write8((sata_bar5 + 0x12C + 0x80 * i), byte); |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 445 | |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 446 | /* Wait 1000ms */ |
| 447 | mdelay(1000); |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 448 | |
Timothy Pearson | 876bdd4 | 2015-06-22 20:57:39 -0500 | [diff] [blame] | 449 | /* Clear Reset Bit */ |
| 450 | byte &= ~0x01; |
| 451 | write8((sata_bar5 + 0x12C + 0x80 * i), byte); |
| 452 | |
| 453 | /* Wait 1ms */ |
| 454 | mdelay(1); |
Timothy Pearson | 5260a44 | 2015-06-22 02:21:29 -0500 | [diff] [blame] | 455 | } |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 456 | } |
Timothy Pearson | 398540f | 2015-06-20 21:31:15 -0500 | [diff] [blame] | 457 | if (sata_ahci_mode) |
| 458 | printk(BIOS_DEBUG, "AHCI device %d is %sready after %i tries\n", |
| 459 | i, |
| 460 | (j == 10) ? "not " : "", |
| 461 | (j == 10) ? j : j + 1); |
| 462 | else |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 463 | printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", |
| 464 | (i / 2) ? "Secondary" : "Primary", |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 465 | (i % 2) ? "Slave" : "Master", |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 466 | (j == 10) ? "not " : "", |
| 467 | (j == 10) ? j : j + 1); |
Timothy Pearson | 398540f | 2015-06-20 21:31:15 -0500 | [diff] [blame] | 468 | } else { |
| 469 | if (sata_ahci_mode) |
| 470 | printk(BIOS_DEBUG, "No AHCI SATA drive on Slot%i\n", i); |
| 471 | else |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 472 | printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", |
| 473 | (i / 2) ? "Secondary" : "Primary", |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 474 | (i % 2) ? "Slave" : "Master", i); |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 475 | } |
| 476 | } |
| 477 | |
Timothy Pearson | 0111459 | 2015-06-22 02:56:10 -0500 | [diff] [blame] | 478 | /* Restore IDE I/O access */ |
| 479 | if (!ide_io_enabled) { |
| 480 | byte = pci_read_config8(ide_dev, 0x04); |
| 481 | byte &= ~0x1; |
| 482 | pci_write_config8(ide_dev, 0x04, byte); |
| 483 | } |
| 484 | |
| 485 | /* Re-enable legacy IDE mode */ |
| 486 | if (ide_legacy_io_enabled) { |
| 487 | byte = pci_read_config8(ide_dev, 0x09); |
| 488 | byte &= ~0x1; |
| 489 | pci_write_config8(ide_dev, 0x09, byte); |
| 490 | } |
| 491 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 492 | /* Below is CIM InitSataLateFar */ |
Timothy Pearson | 0111459 | 2015-06-22 02:56:10 -0500 | [diff] [blame] | 493 | if (sata_ahci_mode) { |
| 494 | /* Disable combined mode */ |
| 495 | byte = pci_read_config8(sm_dev, 0xad); |
| 496 | byte &= ~(1 << 3); |
| 497 | pci_write_config8(sm_dev, 0xad, byte); |
| 498 | } else { |
Timothy Pearson | 14ebf95 | 2015-06-21 16:27:03 -0500 | [diff] [blame] | 499 | /* Enable interrupts from the HBA */ |
| 500 | byte = read8(sata_bar5 + 0x4); |
| 501 | byte |= 1 << 1; |
| 502 | write8((sata_bar5 + 0x4), byte); |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 503 | } |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 504 | |
Timothy Pearson | 14ebf95 | 2015-06-21 16:27:03 -0500 | [diff] [blame] | 505 | /* Clear error status */ |
| 506 | write32((sata_bar5 + 0x130), 0xFFFFFFFF); |
| 507 | write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); |
| 508 | write32((sata_bar5 + 0x230), 0xFFFFFFFF); |
| 509 | write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); |
| 510 | write32((sata_bar5 + 0x330), 0xFFFFFFFF); |
| 511 | write32((sata_bar5 + 0x3b0), 0xFFFFFFFF); |
| 512 | |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 513 | /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 514 | /* ????? why CIM does not set the AcpiGpe0BlkAddr, but use it??? */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 515 | |
| 516 | /* word = 0x0000; */ |
| 517 | /* word = pm_ioread(0x28); */ |
| 518 | /* byte = pm_ioread(0x29); */ |
| 519 | /* word |= byte<<8; */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 520 | /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */ |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 521 | /* write32(word, 0x80000000); */ |
| 522 | } |
| 523 | |
| 524 | static struct pci_operations lops_pci = { |
efdesign98 | 00c8c4a | 2011-07-20 12:37:58 -0600 | [diff] [blame] | 525 | .set_subsystem = pci_dev_set_subsystem, |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 526 | }; |
| 527 | |
| 528 | static struct device_operations sata_ops = { |
| 529 | .read_resources = pci_dev_read_resources, |
| 530 | .set_resources = pci_dev_set_resources, |
| 531 | .enable_resources = pci_dev_enable_resources, |
| 532 | .init = sata_init, |
| 533 | .scan_bus = 0, |
| 534 | .ops_pci = &lops_pci, |
| 535 | }; |
| 536 | |
Stefan Reinauer | 8e96ba2 | 2010-03-16 23:33:29 +0000 | [diff] [blame] | 537 | static const struct pci_driver sata0_driver __pci_driver = { |
Zheng Bao | eff2ffd | 2010-03-16 01:38:54 +0000 | [diff] [blame] | 538 | .ops = &sata_ops, |
| 539 | .vendor = PCI_VENDOR_ID_ATI, |
| 540 | .device = PCI_DEVICE_ID_ATI_SB700_SATA, |
| 541 | }; |
Timothy Pearson | 5d7dc55 | 2015-06-09 18:09:50 -0500 | [diff] [blame] | 542 | |
| 543 | static const struct pci_driver sata1_driver __pci_driver = { |
| 544 | .ops = &sata_ops, |
| 545 | .vendor = PCI_VENDOR_ID_ATI, |
| 546 | .device = PCI_DEVICE_ID_ATI_SB700_SATA_AHCI, |
| 547 | }; |
| 548 | |
| 549 | static const struct pci_driver sata2_driver __pci_driver = { |
| 550 | .ops = &sata_ops, |
| 551 | .vendor = PCI_VENDOR_ID_ATI, |
| 552 | .device = PCI_DEVICE_ID_ATI_SB700_SATA_AHCI_AMD, |
| 553 | }; |