blob: 4ca29e08c59ce2c280d4aec884a3ef02ab5b9a60 [file] [log] [blame]
Zheng Bao7b4a99c2013-11-05 13:58:50 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Zheng Bao7b4a99c2013-11-05 13:58:50 +080014 */
15
Alexandru Gagniuc01e0adf2014-03-29 17:07:26 -050016#include <Proc/Fch/FchPlatform.h>
17#include <Proc/Fch/Fch.h>
Zheng Bao7b4a99c2013-11-05 13:58:50 +080018#include <device/device.h>
19#include "hudson.h"
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +020020#include <AGESA.h>
Zheng Bao7b4a99c2013-11-05 13:58:50 +080021
Kyösti Mälkki38aff1a2017-07-26 00:57:30 +030022#include <northbridge/amd/agesa/state_machine.h>
23
Zheng Bao7b4a99c2013-11-05 13:58:50 +080024extern FCH_DATA_BLOCK InitEnvCfgDefault;
25extern FCH_INTERFACE FchInterfaceDefault;
26extern FCH_RESET_DATA_BLOCK InitResetCfgDefault;
27extern FCH_RESET_INTERFACE FchResetInterfaceDefault;
28
29#define DUMP_FCH_SETTING 0
30
Kyösti Mälkki38aff1a2017-07-26 00:57:30 +030031static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
Zheng Bao7b4a99c2013-11-05 13:58:50 +080032{
Zheng Bao7b4a99c2013-11-05 13:58:50 +080033 *FchParams = InitEnvCfgDefault;
Zheng Bao7b4a99c2013-11-05 13:58:50 +080034
35 FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable;
36 FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable;
37 FchParams->Spi.SpiFastSpeed = InitResetCfgDefault.FastSpeed;
38 FchParams->Spi.WriteSpeed = InitResetCfgDefault.WriteSpeed;
39 FchParams->Spi.SpiMode = InitResetCfgDefault.Mode;
40 FchParams->Spi.AutoMode = InitResetCfgDefault.AutoMode;
41 FchParams->Spi.SpiBurstWrite = InitResetCfgDefault.BurstWrite;
42 FchParams->Sata.SataMode.Sata6AhciCap = (UINT8) InitResetCfgDefault.Sata6AhciCap;
43 FchParams->Misc.Cg2Pll = InitResetCfgDefault.Cg2Pll;
44 FchParams->Sata.SataMode.SataSetMaxGen2 = InitResetCfgDefault.SataSetMaxGen2;
45 FchParams->Sata.SataMode.SataClkMode = InitResetCfgDefault.SataClkMode;
46 FchParams->Sata.SataMode.SataModeReg = InitResetCfgDefault.SataModeReg;
47 FchParams->Sata.SataInternal100Spread = (UINT8) InitResetCfgDefault.SataInternal100Spread;
48 FchParams->Spi.SpiSpeed = InitResetCfgDefault.SpiSpeed;
49 FchParams->Gpp = InitResetCfgDefault.Gpp;
50 FchParams->Gpp.GppFunctionEnable = FchResetInterfaceDefault.GppEnable;
51
52 FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
53 FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
54 FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
55 FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
56 FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
57 FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
58 FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
59 FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
60 FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
61
62 FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
63 FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
64 FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
65 FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
66 FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
67 FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
68 FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
69 FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
70 FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
71 FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
72 FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
73 FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
74 FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
75 FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
76 FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
77 FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
78 FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
79 FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
80 FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
81 FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
82 FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
83 FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
84 FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
85 FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
86 FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
87 FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
88 FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
89
90 FchParams->Sd.SdConfig = FchInterfaceDefault.SdConfig;
91 FchParams->Azalia.AzaliaEnable = FchInterfaceDefault.AzaliaController;
92 FchParams->Ir.IrConfig = FchInterfaceDefault.IrConfig;
93 FchParams->Ab.NbSbGen2 = FchInterfaceDefault.UmiGen2;
94 FchParams->Sata.SataClass = FchInterfaceDefault.SataClass;
95 FchParams->Sata.SataMode.SataEnable = FchInterfaceDefault.SataEnable;
96 FchParams->Sata.SataMode.IdeEnable = FchInterfaceDefault.IdeEnable;
97 FchParams->Sata.SataIdeMode = FchInterfaceDefault.SataIdeMode;
98 FchParams->Usb.Ohci1Enable = FchInterfaceDefault.Ohci1Enable;
99 FchParams->Usb.Ehci1Enable = FchInterfaceDefault.Ohci1Enable;
100 FchParams->Usb.Ohci2Enable = FchInterfaceDefault.Ohci2Enable;
101 FchParams->Usb.Ehci2Enable = FchInterfaceDefault.Ohci2Enable;
102 FchParams->Usb.Ohci3Enable = FchInterfaceDefault.Ohci3Enable;
103 FchParams->Usb.Ehci3Enable = FchInterfaceDefault.Ohci3Enable;
104 FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable;
105 FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail;
106
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200107 FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
108 FchParams->Usb.Xhci1Enable = FALSE;
Zheng Bao7b4a99c2013-11-05 13:58:50 +0800109
110#if DUMP_FCH_SETTING
111 int i;
112
113 for (i = 0; i < sizeof(FchParams); i++) {
114 printk(BIOS_DEBUG, " %02x", ((u8 *) FchParams)[i]);
115 if ((i % 16) == 15)
116 printk(BIOS_DEBUG, "\n");
117 }
118#endif
119}
Kyösti Mälkki38aff1a2017-07-26 00:57:30 +0300120
121AGESA_STATUS fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader)
122{
123 FCH_DATA_BLOCK FchParams;
124
125 /* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */
126 s3_resume_init_data(&FchParams);
127
128 FchParams.StdHeader = StdHeader;
129 FchInitS3EarlyRestore(&FchParams);
130 return AGESA_SUCCESS;
131}
132
133AGESA_STATUS fchs3laterestore(AMD_CONFIG_PARAMS *StdHeader)
134{
135 FCH_DATA_BLOCK FchParams;
136
137 /* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */
138 s3_resume_init_data(&FchParams);
139
140 FchParams.StdHeader = StdHeader;
141 FchInitS3LateRestore(&FchParams);
142
143 return AGESA_SUCCESS;
144}