| Zheng Bao | 7b4a99c | 2013-11-05 13:58:50 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include "FchPlatform.h" |
| 21 | #include "Fch.h" |
| 22 | #include <cpu/amd/agesa/s3_resume.h> |
| 23 | #include <device/device.h> |
| 24 | #include "hudson.h" |
| 25 | #include "AGESA.h" |
| 26 | |
| 27 | extern FCH_DATA_BLOCK InitEnvCfgDefault; |
| 28 | extern FCH_INTERFACE FchInterfaceDefault; |
| 29 | extern FCH_RESET_DATA_BLOCK InitResetCfgDefault; |
| 30 | extern FCH_RESET_INTERFACE FchResetInterfaceDefault; |
| 31 | |
| 32 | #define DUMP_FCH_SETTING 0 |
| 33 | |
| 34 | void s3_resume_init_data(void *data) |
| 35 | { |
| 36 | FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)data; |
| 37 | AMD_CONFIG_PARAMS *StdHeader = FchParams->StdHeader; |
| 38 | |
| 39 | *FchParams = InitEnvCfgDefault; |
| 40 | FchParams->StdHeader = StdHeader; |
| 41 | |
| 42 | FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable; |
| 43 | FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable; |
| 44 | FchParams->Spi.SpiFastSpeed = InitResetCfgDefault.FastSpeed; |
| 45 | FchParams->Spi.WriteSpeed = InitResetCfgDefault.WriteSpeed; |
| 46 | FchParams->Spi.SpiMode = InitResetCfgDefault.Mode; |
| 47 | FchParams->Spi.AutoMode = InitResetCfgDefault.AutoMode; |
| 48 | FchParams->Spi.SpiBurstWrite = InitResetCfgDefault.BurstWrite; |
| 49 | FchParams->Sata.SataMode.Sata6AhciCap = (UINT8) InitResetCfgDefault.Sata6AhciCap; |
| 50 | FchParams->Misc.Cg2Pll = InitResetCfgDefault.Cg2Pll; |
| 51 | FchParams->Sata.SataMode.SataSetMaxGen2 = InitResetCfgDefault.SataSetMaxGen2; |
| 52 | FchParams->Sata.SataMode.SataClkMode = InitResetCfgDefault.SataClkMode; |
| 53 | FchParams->Sata.SataMode.SataModeReg = InitResetCfgDefault.SataModeReg; |
| 54 | FchParams->Sata.SataInternal100Spread = (UINT8) InitResetCfgDefault.SataInternal100Spread; |
| 55 | FchParams->Spi.SpiSpeed = InitResetCfgDefault.SpiSpeed; |
| 56 | FchParams->Gpp = InitResetCfgDefault.Gpp; |
| 57 | FchParams->Gpp.GppFunctionEnable = FchResetInterfaceDefault.GppEnable; |
| 58 | |
| 59 | FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; |
| 60 | FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; |
| 61 | FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; |
| 62 | FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; |
| 63 | FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; |
| 64 | FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; |
| 65 | FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; |
| 66 | FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; |
| 67 | FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; |
| 68 | |
| 69 | FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; |
| 70 | FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; |
| 71 | FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; |
| 72 | FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; |
| 73 | FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; |
| 74 | FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; |
| 75 | FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; |
| 76 | FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; |
| 77 | FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; |
| 78 | FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; |
| 79 | FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; |
| 80 | FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; |
| 81 | FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; |
| 82 | FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; |
| 83 | FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; |
| 84 | FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; |
| 85 | FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; |
| 86 | FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; |
| 87 | FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; |
| 88 | FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; |
| 89 | FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; |
| 90 | FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; |
| 91 | FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; |
| 92 | FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; |
| 93 | FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; |
| 94 | FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; |
| 95 | FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; |
| 96 | |
| 97 | FchParams->Sd.SdConfig = FchInterfaceDefault.SdConfig; |
| 98 | FchParams->Azalia.AzaliaEnable = FchInterfaceDefault.AzaliaController; |
| 99 | FchParams->Ir.IrConfig = FchInterfaceDefault.IrConfig; |
| 100 | FchParams->Ab.NbSbGen2 = FchInterfaceDefault.UmiGen2; |
| 101 | FchParams->Sata.SataClass = FchInterfaceDefault.SataClass; |
| 102 | FchParams->Sata.SataMode.SataEnable = FchInterfaceDefault.SataEnable; |
| 103 | FchParams->Sata.SataMode.IdeEnable = FchInterfaceDefault.IdeEnable; |
| 104 | FchParams->Sata.SataIdeMode = FchInterfaceDefault.SataIdeMode; |
| 105 | FchParams->Usb.Ohci1Enable = FchInterfaceDefault.Ohci1Enable; |
| 106 | FchParams->Usb.Ehci1Enable = FchInterfaceDefault.Ohci1Enable; |
| 107 | FchParams->Usb.Ohci2Enable = FchInterfaceDefault.Ohci2Enable; |
| 108 | FchParams->Usb.Ehci2Enable = FchInterfaceDefault.Ohci2Enable; |
| 109 | FchParams->Usb.Ohci3Enable = FchInterfaceDefault.Ohci3Enable; |
| 110 | FchParams->Usb.Ehci3Enable = FchInterfaceDefault.Ohci3Enable; |
| 111 | FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; |
| 112 | FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; |
| 113 | |
| 114 | #if !CONFIG_HUDSON_XHCI_ENABLE |
| 115 | FchParams->Usb.Xhci0Enable = FALSE; |
| 116 | #endif |
| 117 | FchParams->Usb.Xhci1Enable = FALSE; |
| 118 | |
| 119 | #if DUMP_FCH_SETTING |
| 120 | int i; |
| 121 | |
| 122 | for (i = 0; i < sizeof(FchParams); i++) { |
| 123 | printk(BIOS_DEBUG, " %02x", ((u8 *) FchParams)[i]); |
| 124 | if ((i % 16) == 15) |
| 125 | printk(BIOS_DEBUG, "\n"); |
| 126 | } |
| 127 | #endif |
| 128 | } |