Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 16 | #include <arch/cpu.h> |
| 17 | #include <arch/early_variables.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 18 | #include <arch/symbols.h> |
| 19 | #include <assert.h> |
| 20 | #include <cpu/x86/mtrr.h> |
Naresh G Solanki | 79239b7 | 2016-11-16 21:34:41 +0530 | [diff] [blame] | 21 | #include <cpu/x86/msr.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 22 | #include <cbmem.h> |
| 23 | #include <chip.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 24 | #include <console/console.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 25 | #include <device/pci_def.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 26 | #include <fsp/util.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 27 | #include <fsp/memmap.h> |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 28 | #include <intelblocks/pmclib.h> |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 29 | #include <memory_info.h> |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 30 | #include <smbios.h> |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 31 | #include <soc/intel/common/smbios.h> |
Naresh G Solanki | 79239b7 | 2016-11-16 21:34:41 +0530 | [diff] [blame] | 32 | #include <soc/msr.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
| 34 | #include <soc/pm.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 35 | #include <soc/romstage.h> |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 36 | #include <string.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 37 | #include <timestamp.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 38 | #include <security/vboot/vboot_common.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 39 | |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 40 | #define FSP_SMBIOS_MEMORY_INFO_GUID \ |
| 41 | { \ |
| 42 | 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ |
| 43 | 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ |
| 44 | } |
| 45 | |
Subrata Banik | 54fa28e | 2018-02-07 14:59:34 +0530 | [diff] [blame] | 46 | /* Memory Channel Present Status */ |
| 47 | enum { |
| 48 | CHANNEL_NOT_PRESENT, |
| 49 | CHANNEL_DISABLED, |
| 50 | CHANNEL_PRESENT |
| 51 | }; |
| 52 | |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 53 | /* Save the DIMM information for SMBIOS table 17 */ |
| 54 | static void save_dimm_info(void) |
| 55 | { |
| 56 | int channel, dimm, dimm_max, index; |
| 57 | size_t hob_size; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 58 | uint8_t ddr_type; |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 59 | const CONTROLLER_INFO *ctrlr_info; |
| 60 | const CHANNEL_INFO *channel_info; |
| 61 | const DIMM_INFO *src_dimm; |
| 62 | struct dimm_info *dest_dimm; |
| 63 | struct memory_info *mem_info; |
| 64 | const MEMORY_INFO_DATA_HOB *memory_info_hob; |
Subrata Banik | 54fa28e | 2018-02-07 14:59:34 +0530 | [diff] [blame] | 65 | const uint8_t smbios_memory_info_guid[16] = |
| 66 | FSP_SMBIOS_MEMORY_INFO_GUID; |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 67 | |
| 68 | /* Locate the memory info HOB, presence validated by raminit */ |
| 69 | memory_info_hob = |
| 70 | fsp_find_extension_hob_by_guid(smbios_memory_info_guid, |
| 71 | &hob_size); |
Subrata Banik | 54fa28e | 2018-02-07 14:59:34 +0530 | [diff] [blame] | 72 | if (memory_info_hob == NULL || hob_size == 0) { |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 73 | printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); |
| 74 | return; |
| 75 | } |
| 76 | |
| 77 | /* |
| 78 | * Allocate CBMEM area for DIMM information used to populate SMBIOS |
| 79 | * table 17 |
| 80 | */ |
| 81 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 82 | if (mem_info == NULL) { |
| 83 | printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); |
| 84 | return; |
| 85 | } |
| 86 | memset(mem_info, 0, sizeof(*mem_info)); |
| 87 | |
| 88 | /* Describe the first N DIMMs in the system */ |
| 89 | index = 0; |
| 90 | dimm_max = ARRAY_SIZE(mem_info->dimm); |
| 91 | ctrlr_info = &memory_info_hob->Controller[0]; |
Nico Huber | 9dc62ea | 2017-07-19 15:45:14 +0200 | [diff] [blame] | 92 | for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { |
Balaji Manigandan B | bd55c02 | 2017-09-22 14:27:56 +0530 | [diff] [blame] | 93 | channel_info = &ctrlr_info->ChannelInfo[channel]; |
Subrata Banik | 54fa28e | 2018-02-07 14:59:34 +0530 | [diff] [blame] | 94 | if (channel_info->Status != CHANNEL_PRESENT) |
Nico Huber | 9dc62ea | 2017-07-19 15:45:14 +0200 | [diff] [blame] | 95 | continue; |
| 96 | for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { |
Balaji Manigandan B | bd55c02 | 2017-09-22 14:27:56 +0530 | [diff] [blame] | 97 | src_dimm = &channel_info->DimmInfo[dimm]; |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 98 | dest_dimm = &mem_info->dimm[index]; |
| 99 | |
Nico Huber | 9dc62ea | 2017-07-19 15:45:14 +0200 | [diff] [blame] | 100 | if (src_dimm->Status != DIMM_PRESENT) |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 101 | continue; |
| 102 | |
Elyes HAOUAS | 0ce41f1 | 2018-11-13 10:03:31 +0100 | [diff] [blame] | 103 | switch (memory_info_hob->MemoryType) { |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 104 | case MRC_DDR_TYPE_DDR4: |
Elyes HAOUAS | 28114ae | 2018-11-14 17:51:00 +0100 | [diff] [blame] | 105 | ddr_type = MEMORY_TYPE_DDR4; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 106 | break; |
| 107 | case MRC_DDR_TYPE_DDR3: |
Elyes HAOUAS | 28114ae | 2018-11-14 17:51:00 +0100 | [diff] [blame] | 108 | ddr_type = MEMORY_TYPE_DDR3; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 109 | break; |
| 110 | case MRC_DDR_TYPE_LPDDR3: |
Elyes HAOUAS | 28114ae | 2018-11-14 17:51:00 +0100 | [diff] [blame] | 111 | ddr_type = MEMORY_TYPE_LPDDR3; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 112 | break; |
| 113 | default: |
Elyes HAOUAS | 28114ae | 2018-11-14 17:51:00 +0100 | [diff] [blame] | 114 | ddr_type = MEMORY_TYPE_UNKNOWN; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 115 | break; |
| 116 | } |
| 117 | |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 118 | /* Populate the DIMM information */ |
| 119 | dimm_info_fill(dest_dimm, |
| 120 | src_dimm->DimmCapacity, |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 121 | ddr_type, |
Balaji Manigandan B | bd55c02 | 2017-09-22 14:27:56 +0530 | [diff] [blame] | 122 | memory_info_hob->ConfiguredMemoryClockSpeed, |
Francois Toguo | 993f68a | 2019-02-04 17:05:51 -0800 | [diff] [blame] | 123 | src_dimm->RankInDimm, |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 124 | channel_info->ChannelId, |
| 125 | src_dimm->DimmId, |
| 126 | (const char *)src_dimm->ModulePartNum, |
| 127 | sizeof(src_dimm->ModulePartNum), |
| 128 | memory_info_hob->DataWidth); |
| 129 | index++; |
| 130 | } |
| 131 | } |
| 132 | mem_info->dimm_cnt = index; |
| 133 | printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); |
| 134 | } |
| 135 | |
Aaron Durbin | 79f0741 | 2017-04-16 21:49:29 -0500 | [diff] [blame] | 136 | asmlinkage void car_stage_entry(void) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 137 | { |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 138 | bool s3wake; |
| 139 | struct postcar_frame pcf; |
| 140 | uintptr_t top_of_ram; |
| 141 | struct chipset_power_state *ps; |
| 142 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 143 | console_init(); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 144 | |
| 145 | /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ |
| 146 | systemagent_early_init(); |
| 147 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 148 | ps = pmc_get_power_state(); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 149 | timestamp_add_now(TS_START_ROMSTAGE); |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 150 | s3wake = pmc_fill_power_state(ps) == ACPI_S3; |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 151 | fsp_memory_init(s3wake); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 152 | pmc_set_disb(); |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 153 | if (!s3wake) |
| 154 | save_dimm_info(); |
Aaron Durbin | 4dc9fb0 | 2017-07-11 17:29:02 -0600 | [diff] [blame] | 155 | if (postcar_frame_init(&pcf, 1*KiB)) |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 156 | die("Unable to initialize postcar frame.\n"); |
| 157 | |
| 158 | /* |
| 159 | * We need to make sure ramstage will be run cached. At this |
| 160 | * point exact location of ramstage in cbmem is not known. |
| 161 | * Instruct postcar to cache 16 megs under cbmem top which is |
| 162 | * a safe bet to cover ramstage. |
| 163 | */ |
| 164 | top_of_ram = (uintptr_t) cbmem_top(); |
| 165 | printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); |
| 166 | top_of_ram -= 16*MiB; |
| 167 | postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); |
| 168 | |
| 169 | if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { |
| 170 | void *smm_base; |
| 171 | size_t smm_size; |
| 172 | uintptr_t tseg_base; |
| 173 | |
| 174 | /* |
| 175 | * Cache the TSEG region at the top of ram. This region is |
| 176 | * not restricted to SMM mode until SMM has been relocated. |
| 177 | * By setting the region to cacheable it provides faster access |
| 178 | * when relocating the SMM handler as well as using the TSEG |
| 179 | * region for other purposes. |
| 180 | */ |
| 181 | smm_region(&smm_base, &smm_size); |
| 182 | tseg_base = (uintptr_t)smm_base; |
| 183 | postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, |
| 184 | MTRR_TYPE_WRBACK); |
| 185 | } |
| 186 | |
| 187 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 6ea6775 | 2018-05-27 14:37:52 +0200 | [diff] [blame] | 188 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 189 | |
Aaron Durbin | 79f0741 | 2017-04-16 21:49:29 -0500 | [diff] [blame] | 190 | run_postcar_phase(&pcf); |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 191 | } |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 192 | |
Naresh G Solanki | 79239b7 | 2016-11-16 21:34:41 +0530 | [diff] [blame] | 193 | static void cpu_flex_override(FSP_M_CONFIG *m_cfg) |
| 194 | { |
| 195 | msr_t flex_ratio; |
| 196 | m_cfg->CpuRatioOverride = 1; |
| 197 | /* |
| 198 | * Set cpuratio to that value set in bootblock, This will ensure FSPM |
| 199 | * knows the intended flex ratio. |
| 200 | */ |
| 201 | flex_ratio = rdmsr(MSR_FLEX_RATIO); |
| 202 | m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; |
| 203 | } |
| 204 | |
Aamir Bohra | 6375512 | 2017-02-06 21:48:48 +0530 | [diff] [blame] | 205 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, |
| 206 | const struct soc_intel_skylake_config *config) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 207 | { |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 208 | int i; |
| 209 | uint32_t mask = 0; |
| 210 | |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 211 | /* |
| 212 | * Set IGD stolen size to 64MB. The FBC hardware for skylake does not |
| 213 | * have access to the bios_reserved range so it always assumes 8MB is |
| 214 | * used and so the kernel will avoid the last 8MB of the stolen window. |
| 215 | * With the default stolen size of 32MB(-8MB) there is not enough space |
| 216 | * for FBC to work with a high resolution panel. |
| 217 | */ |
| 218 | m_cfg->IgdDvmt50PreAlloc = 2; |
| 219 | m_cfg->MmioSize = 0x800; /* 2GB in MB */ |
| 220 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 221 | m_cfg->IedSize = CONFIG_IED_REGION_SIZE; |
| 222 | m_cfg->ProbelessTrace = config->ProbelessTrace; |
Subrata Banik | 3214bc4 | 2017-07-10 13:17:09 +0530 | [diff] [blame] | 223 | m_cfg->SaGv = config->SaGv; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 224 | m_cfg->UserBd = BOARD_TYPE_ULT_ULX; |
| 225 | m_cfg->RMT = config->Rmt; |
Shaunak Saha | ef250c4 | 2018-08-31 12:49:08 -0700 | [diff] [blame] | 226 | m_cfg->CmdTriStateDis = config->CmdTriStateDis; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 227 | m_cfg->DdrFreqLimit = config->DdrFreqLimit; |
Nico Huber | 6275e34 | 2018-11-21 00:11:35 +0100 | [diff] [blame] | 228 | m_cfg->VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX); |
Robbie Zhang | e65affa | 2017-02-13 12:07:53 -0800 | [diff] [blame] | 229 | m_cfg->PrmrrSize = config->PrmrrSize; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 230 | for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { |
| 231 | if (config->PcieRpEnable[i]) |
| 232 | mask |= (1<<i); |
| 233 | } |
| 234 | m_cfg->PcieRpEnableMask = mask; |
Naresh G Solanki | 79239b7 | 2016-11-16 21:34:41 +0530 | [diff] [blame] | 235 | |
| 236 | cpu_flex_override(m_cfg); |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 237 | |
| 238 | if (!config->ignore_vtd) { |
| 239 | m_cfg->PchHpetBdfValid = 1; |
| 240 | m_cfg->PchHpetBusNumber = 250; |
| 241 | m_cfg->PchHpetDeviceNumber = 15; |
| 242 | m_cfg->PchHpetFunctionNumber = 0; |
| 243 | } |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 244 | } |
| 245 | |
Andrey Petrov | f796c6e | 2016-11-18 14:57:51 -0800 | [diff] [blame] | 246 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 247 | { |
Aamir Bohra | 6375512 | 2017-02-06 21:48:48 +0530 | [diff] [blame] | 248 | const struct device *dev; |
| 249 | const struct soc_intel_skylake_config *config; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 250 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 251 | FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 252 | |
Aamir Bohra | 6375512 | 2017-02-06 21:48:48 +0530 | [diff] [blame] | 253 | dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); |
| 254 | config = dev->chip_info; |
| 255 | |
| 256 | soc_memory_init_params(m_cfg, config); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 257 | |
Duncan Laurie | e0b5795 | 2017-08-10 16:27:48 -0700 | [diff] [blame] | 258 | /* Skip creating Management Engine MBP HOB */ |
| 259 | m_t_cfg->SkipMbpHob = 0x01; |
| 260 | |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 261 | /* Enable DMI Virtual Channel for ME */ |
| 262 | m_t_cfg->DmiVcm = 0x01; |
| 263 | |
| 264 | /* Enable Sending DID to ME */ |
| 265 | m_t_cfg->SendDidMsg = 0x01; |
| 266 | m_t_cfg->DidInitStat = 0x01; |
| 267 | |
Aamir Bohra | 6375512 | 2017-02-06 21:48:48 +0530 | [diff] [blame] | 268 | /* DCI and TraceHub configs */ |
| 269 | m_t_cfg->PchDciEn = config->PchDciEn; |
| 270 | m_cfg->EnableTraceHub = config->EnableTraceHub; |
| 271 | m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; |
| 272 | m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; |
| 273 | |
Naresh G Solanki | ff48b3b | 2017-07-12 23:01:26 +0530 | [diff] [blame] | 274 | /* Enable SMBus controller based on config */ |
| 275 | m_cfg->SmbusEnable = config->SmbusEnable; |
| 276 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 277 | mainboard_memory_init_params(mupd); |
| 278 | } |
| 279 | |
Pratik Prajapati | ffc934d | 2016-11-18 14:36:34 -0800 | [diff] [blame] | 280 | void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, |
| 281 | struct mma_config_param *mma_cfg) |
| 282 | { |
| 283 | /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ |
| 284 | assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); |
| 285 | |
| 286 | memory_cfg->MmaTestContentPtr = |
| 287 | (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); |
| 288 | memory_cfg->MmaTestContentSize = |
| 289 | region_device_sz(&mma_cfg->test_content); |
| 290 | memory_cfg->MmaTestConfigPtr = |
| 291 | (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); |
| 292 | memory_cfg->MmaTestConfigSize = |
| 293 | region_device_sz(&mma_cfg->test_param); |
| 294 | memory_cfg->MrcFastBoot = 0x00; |
| 295 | memory_cfg->SaGv = 0x02; |
| 296 | } |
| 297 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 298 | __weak void mainboard_memory_init_params(FSPM_UPD *mupd) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 299 | { |
| 300 | /* Do nothing */ |
| 301 | } |