Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 5 | * Copyright (C) 2015-2018 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 15 | */ |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 16 | #include <device/pci_ops.h> |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 17 | #include <chip.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci_def.h> |
Subrata Banik | bffff54 | 2017-11-09 15:07:44 +0530 | [diff] [blame] | 20 | #include <intelblocks/cse.h> |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 21 | #include <intelblocks/fast_spi.h> |
Bora Guvendik | 43c3109 | 2017-04-11 16:05:23 -0700 | [diff] [blame] | 22 | #include <intelblocks/itss.h> |
Ravi Sarawadi | 1483d1f | 2017-09-28 17:06:01 -0700 | [diff] [blame] | 23 | #include <intelblocks/lpc_lib.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 24 | #include <intelblocks/p2sb.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 25 | #include <intelblocks/pcr.h> |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 26 | #include <intelblocks/pmclib.h> |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 27 | #include <intelblocks/rtc.h> |
Aamir Bohra | 502131a | 2017-04-19 22:34:25 +0530 | [diff] [blame] | 28 | #include <intelblocks/smbus.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 29 | #include <intelblocks/tco.h> |
Subrata Banik | e4a8537 | 2016-07-24 00:36:12 +0530 | [diff] [blame] | 30 | #include <soc/bootblock.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 31 | #include <soc/iomap.h> |
Rizwan Qureshi | cf73c13 | 2016-08-04 20:01:12 +0530 | [diff] [blame] | 32 | #include <soc/p2sb.h> |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 33 | #include <soc/pch.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 34 | #include <soc/pci_devs.h> |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 35 | #include <soc/pcr_ids.h> |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 36 | #include <soc/pm.h> |
| 37 | #include <soc/pmc.h> |
| 38 | #include <soc/smbus.h> |
| 39 | |
Subrata Banik | efbfdd2 | 2018-02-26 14:49:00 +0530 | [diff] [blame] | 40 | #define PCR_DMI_DMICTL 0x2234 |
| 41 | #define PCR_DMI_DMICTL_SRLOCK (1 << 31) |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 42 | #define PCR_DMI_ACPIBA 0x27B4 |
| 43 | #define PCR_DMI_ACPIBDID 0x27B8 |
| 44 | #define PCR_DMI_PMBASEA 0x27AC |
| 45 | #define PCR_DMI_PMBASEC 0x27B0 |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 46 | |
Subrata Banik | e4a8537 | 2016-07-24 00:36:12 +0530 | [diff] [blame] | 47 | void bootblock_pch_early_init(void) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 48 | { |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 49 | fast_spi_early_init(SPI_BASE_ADDRESS); |
Subrata Banik | 7837c20 | 2018-05-07 17:13:40 +0530 | [diff] [blame] | 50 | p2sb_enable_bar(); |
| 51 | p2sb_configure_hpet(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 52 | } |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 53 | |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 54 | static void soc_config_acpibase(void) |
| 55 | { |
| 56 | uint32_t reg32; |
| 57 | |
| 58 | /* Disable ABASE in PMC Device first before changing Base Address */ |
| 59 | reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); |
| 60 | pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); |
| 61 | |
| 62 | /* Program ACPI Base */ |
| 63 | pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); |
| 64 | |
| 65 | /* Enable ACPI in PMC */ |
| 66 | pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); |
| 67 | |
| 68 | /* |
| 69 | * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] |
| 70 | * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] |
| 71 | */ |
| 72 | reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 73 | pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); |
Nico Huber | 9413cb5 | 2017-07-06 15:06:37 +0200 | [diff] [blame] | 74 | if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) |
| 75 | pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); |
| 76 | else |
| 77 | pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0); |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 78 | } |
| 79 | |
| 80 | static void soc_config_pwrmbase(void) |
| 81 | { |
| 82 | uint32_t reg32; |
| 83 | |
| 84 | /* Disable PWRMBASE in PMC Device first before changing Base address */ |
| 85 | reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); |
| 86 | pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~PWRM_EN); |
| 87 | |
| 88 | /* Program PWRM Base */ |
| 89 | pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); |
| 90 | |
| 91 | /* Enable PWRM in PMC */ |
| 92 | pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | PWRM_EN); |
| 93 | |
| 94 | /* |
| 95 | * Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] |
| 96 | * to the same value programmed in PMC PCI Offset 48h bit[31:16], |
| 97 | * this has an implication of making sure the PWRMBASE to be |
| 98 | * 64KB aligned. |
| 99 | * |
| 100 | * Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] |
| 101 | * to the value programmed in PMC PCI Offset 48h bit[31:16], this has an |
Lee Leahy | b439a92 | 2017-03-16 16:44:36 -0700 | [diff] [blame] | 102 | * implication of making sure the memory allocated to PWRMBASE to be |
| 103 | * 64KB in size. |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 104 | */ |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 105 | pcr_write32(PID_DMI, PCR_DMI_PMBASEA, |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 106 | ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | |
| 107 | (PCH_PWRM_BASE_ADDRESS >> 16))); |
Nico Huber | 9413cb5 | 2017-07-06 15:06:37 +0200 | [diff] [blame] | 108 | if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) |
| 109 | pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8); |
| 110 | else |
| 111 | pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0); |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 112 | } |
| 113 | |
Subrata Banik | efbfdd2 | 2018-02-26 14:49:00 +0530 | [diff] [blame] | 114 | static int pch_check_decode_enable(void) |
| 115 | { |
| 116 | uint32_t dmi_control; |
| 117 | |
| 118 | /* |
| 119 | * This cycle decoding is only allowed to set when |
| 120 | * DMICTL.SRLOCK is 0. |
| 121 | */ |
| 122 | dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); |
| 123 | if (dmi_control & PCR_DMI_DMICTL_SRLOCK) |
| 124 | return -1; |
| 125 | return 0; |
| 126 | } |
| 127 | |
Teo Boon Tiong | 544dac6 | 2016-11-10 01:21:23 +0800 | [diff] [blame] | 128 | void pch_early_iorange_init(void) |
| 129 | { |
Subrata Banik | efbfdd2 | 2018-02-26 14:49:00 +0530 | [diff] [blame] | 130 | uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | |
| 131 | LPC_IOE_EC_62_66; |
| 132 | |
Teo Boon Tiong | 544dac6 | 2016-11-10 01:21:23 +0800 | [diff] [blame] | 133 | /* IO Decode Range */ |
Subrata Banik | efbfdd2 | 2018-02-26 14:49:00 +0530 | [diff] [blame] | 134 | if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) |
| 135 | lpc_io_setup_comm_a_b(); |
Teo Boon Tiong | 544dac6 | 2016-11-10 01:21:23 +0800 | [diff] [blame] | 136 | |
| 137 | /* IO Decode Enable */ |
Subrata Banik | efbfdd2 | 2018-02-26 14:49:00 +0530 | [diff] [blame] | 138 | if (pch_check_decode_enable() == 0) { |
| 139 | io_enables = lpc_enable_fixed_io_ranges(io_enables); |
| 140 | /* |
| 141 | * As per PCH BWG 2.5.16. |
| 142 | * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same |
| 143 | * value program in LPC PCI offset 82h. |
| 144 | */ |
| 145 | pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); |
| 146 | } |
Nico Huber | c587b97 | 2017-07-06 15:02:48 +0200 | [diff] [blame] | 147 | |
| 148 | /* Program generic IO Decode Range */ |
| 149 | pch_enable_lpc(); |
Teo Boon Tiong | 544dac6 | 2016-11-10 01:21:23 +0800 | [diff] [blame] | 150 | } |
| 151 | |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 152 | void pch_early_init(void) |
| 153 | { |
| 154 | /* |
| 155 | * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, |
| 156 | * GPE0_STS, GPE0_EN registers. |
| 157 | */ |
| 158 | soc_config_acpibase(); |
| 159 | |
| 160 | /* |
| 161 | * Enabling PWRM Base for accessing |
| 162 | * Global Reset Cause Register. |
| 163 | */ |
| 164 | soc_config_pwrmbase(); |
| 165 | |
| 166 | /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 167 | tco_configure(); |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 168 | |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 169 | /* Program SMBUS_BASE_ADDRESS and Enable it */ |
Aamir Bohra | 502131a | 2017-04-19 22:34:25 +0530 | [diff] [blame] | 170 | smbus_common_init(); |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 171 | |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 172 | /* Set up GPE configuration */ |
| 173 | pmc_gpe_init(); |
| 174 | |
Subrata Banik | e0268d3 | 2017-03-09 13:56:17 +0530 | [diff] [blame] | 175 | enable_rtc_upper_bank(); |
Subrata Banik | 29f8708 | 2016-10-13 18:05:04 +0530 | [diff] [blame] | 176 | |
Subrata Banik | bffff54 | 2017-11-09 15:07:44 +0530 | [diff] [blame] | 177 | /* initialize Heci interface */ |
| 178 | heci_init(HECI1_BASE_ADDRESS); |
Naresh G Solanki | ecd9a94 | 2016-08-11 14:56:28 +0530 | [diff] [blame] | 179 | } |