Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of |
| 11 | * the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 21 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 23 | #include <arch/ioapic.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 24 | #include <console/console.h> |
| 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
| 28 | #include <device/pci_def.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 29 | #include <pc80/i8254.h> |
| 30 | #include <pc80/i8259.h> |
| 31 | #include <pc80/isa-dma.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 32 | |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 33 | #include <soc/baytrail.h> |
| 34 | #include <soc/iomap.h> |
| 35 | #include <soc/irq.h> |
| 36 | #include <soc/lpc.h> |
| 37 | #include <soc/nvs.h> |
| 38 | #include <soc/acpi.h> |
| 39 | #include <soc/pci_devs.h> |
| 40 | #include <soc/pmc.h> |
| 41 | #include <soc/ramstage.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 42 | #include "chip.h" |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 43 | #include <arch/acpi.h> |
| 44 | #include <arch/acpigen.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 45 | |
| 46 | #define ENABLE_ACPI_MODE_IN_COREBOOT 0 |
| 47 | #define TEST_SMM_FLASH_LOCKDOWN 0 |
| 48 | |
| 49 | typedef struct soc_intel_fsp_baytrail_config config_t; |
| 50 | |
| 51 | static inline void |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 52 | add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 53 | { |
| 54 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 55 | } |
| 56 | |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 57 | static void sc_add_mmio_resources(struct device *dev) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 58 | { |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 59 | add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); |
| 60 | add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); |
| 61 | add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); |
| 62 | add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); |
| 63 | add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); |
| 64 | add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); |
| 65 | add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); |
| 66 | add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); |
| 67 | add_mmio_resource(dev, 0xfff, 0xffffffff - CONFIG_VIRTUAL_ROM_SIZE + 1, |
| 68 | CONFIG_VIRTUAL_ROM_SIZE); /* BIOS ROM */ |
| 69 | add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ |
| 70 | } |
| 71 | |
| 72 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 73 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 74 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 75 | |
| 76 | static void sc_enable_ioapic(struct device *dev) |
| 77 | { |
| 78 | int i; |
| 79 | u32 reg32; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 80 | volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR); |
| 81 | volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10); |
| 82 | u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 83 | |
| 84 | /* |
| 85 | * Enable ACPI I/O and power management. |
| 86 | * Set SCI IRQ to IRQ9 |
| 87 | */ |
| 88 | write32(ilb_base + ILB_OIC, 0x100); /* AEN */ |
Kevin Paul Herbert | 4104e6c | 2015-02-25 00:36:51 -0800 | [diff] [blame] | 89 | reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ |
| 90 | write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 91 | |
| 92 | *ioapic_index = 0; |
| 93 | *ioapic_data = (1 << 25); |
| 94 | |
| 95 | /* affirm full set of redirection table entries ("write once") */ |
| 96 | *ioapic_index = 1; |
| 97 | reg32 = *ioapic_data; |
| 98 | *ioapic_index = 1; |
| 99 | *ioapic_data = reg32; |
| 100 | |
| 101 | *ioapic_index = 0; |
| 102 | reg32 = *ioapic_data; |
| 103 | printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); |
| 104 | if (reg32 != (1 << 25)) |
| 105 | die("APIC Error\n"); |
| 106 | |
| 107 | printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); |
| 108 | for (i=0; i<3; i++) { |
| 109 | *ioapic_index = i; |
| 110 | printk(BIOS_SPEW, " reg 0x%04x:", i); |
| 111 | reg32 = *ioapic_data; |
| 112 | printk(BIOS_SPEW, " 0x%08x\n", reg32); |
| 113 | } |
| 114 | |
| 115 | *ioapic_index = 3; /* Select Boot Configuration register. */ |
| 116 | *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ |
| 117 | } |
| 118 | |
| 119 | static void sc_enable_serial_irqs(struct device *dev) |
| 120 | { |
| 121 | #ifdef SETUPSERIQ /* NOT defined. Remove when the TODO is done. */ |
| 122 | /* |
| 123 | * TODO: SERIRQ seems to have a number of problems on baytrail. |
| 124 | * With it enabled, we get some spurious interrupts (ps2) |
| 125 | * in seabios. It also caused IOCHK# NMIs. Remove it |
| 126 | * until we understand how it needs to be configured. |
| 127 | */ |
| 128 | u8 reg8; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 129 | u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 130 | |
| 131 | /* |
| 132 | * Disable the IOCHK# NMI. Let the NMI handler enable it if it needs. |
| 133 | */ |
| 134 | reg8 = inb(0x61); |
| 135 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 136 | reg8 |= (1 << 3); /* IOCHK# NMI Disable for now */ |
| 137 | outb(reg8, 0x61); |
| 138 | |
| 139 | write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); |
| 140 | write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); |
| 141 | |
| 142 | #if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) |
| 143 | /* |
| 144 | * SoC requires that the System BIOS first set the SERIRQ logic to |
| 145 | * continuous mode operation for at least one frame before switching |
| 146 | * it into quiet mode operation. |
| 147 | */ |
| 148 | outb(0x00, 0xED); /* I/O Delay to get the 1 frame */ |
| 149 | write8(ibase + ILB_SERIRQ_CNTL, SCNT_QUIET_MODE); |
| 150 | #endif |
| 151 | #endif /* DON'T SET UP IRQS */ |
| 152 | } |
| 153 | |
| 154 | /* |
| 155 | * Write PCI config space IRQ assignments. PCI devices have the INT_LINE |
| 156 | * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing |
| 157 | * information to operating systems and drivers. The INT_PIN register is |
| 158 | * generally read only and reports which interrupt pin A - D it uses. The |
| 159 | * INT_LINE register is configurable and reports which IRQ (generally the |
| 160 | * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling |
| 161 | * on devices that are downstream on a PCI bridge into account. |
| 162 | * |
| 163 | * This function will loop through all enabled PCI devices and program the |
| 164 | * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it |
| 165 | * uses. It then configures each interrupt in the pic to be level triggered. |
| 166 | */ |
| 167 | static void write_pci_config_irqs(void) |
| 168 | { |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 169 | struct device *irq_dev; |
| 170 | struct device *targ_dev; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 171 | uint8_t int_line = 0; |
| 172 | uint8_t original_int_pin = 0; |
| 173 | uint8_t new_int_pin = 0; |
| 174 | uint16_t current_bdf = 0; |
| 175 | uint16_t parent_bdf = 0; |
| 176 | uint8_t pirq = 0; |
| 177 | uint8_t device_num = 0; |
| 178 | const struct baytrail_irq_route *ir = &global_baytrail_irq_route; |
| 179 | |
| 180 | if (ir == NULL) { |
| 181 | printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" |
| 182 | " 'global_baytrail_irq_route' structure does not exist\n"); |
| 183 | return; |
| 184 | } |
| 185 | |
| 186 | /* |
| 187 | * Loop through all enabled devices and program their |
| 188 | * INT_LINE, INT_PIN registers from values taken from |
| 189 | * the Interrupt Route registers in the ILB |
| 190 | */ |
| 191 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); |
Elyes HAOUAS | 4a83f1c | 2016-08-25 21:07:59 +0200 | [diff] [blame] | 192 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 193 | |
| 194 | if ((irq_dev->path.type != DEVICE_PATH_PCI) || |
| 195 | (!irq_dev->enabled)) |
| 196 | continue; |
| 197 | |
| 198 | current_bdf = irq_dev->path.pci.devfn | |
| 199 | irq_dev->bus->secondary << 8; |
| 200 | |
| 201 | /* |
| 202 | * Step 1: Get the INT_PIN and device structure to look for |
| 203 | * in the pirq_data table defined in the mainboard directory. |
| 204 | */ |
| 205 | targ_dev = NULL; |
| 206 | new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); |
| 207 | if (targ_dev == NULL || new_int_pin < 1) |
| 208 | continue; |
| 209 | |
Martin Roth | ffcd939 | 2015-12-07 16:50:47 -0700 | [diff] [blame] | 210 | /* |
| 211 | * Adjust the INT routing for the PCIe root ports |
| 212 | * See 'Interrupt Generated for INT[A-D] Interrupts' |
| 213 | * Table 241 in Document Number: 538136, Rev. 3.9 |
| 214 | */ |
| 215 | if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV && |
| 216 | targ_dev != irq_dev) |
| 217 | new_int_pin = ((new_int_pin - 1 + |
| 218 | PCI_FUNC(targ_dev->path.pci.devfn)) % 4) + 1; |
| 219 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 220 | /* Get the original INT_PIN for record keeping */ |
| 221 | original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 222 | |
| 223 | parent_bdf = targ_dev->path.pci.devfn |
| 224 | | targ_dev->bus->secondary << 8; |
| 225 | device_num = PCI_SLOT(parent_bdf); |
| 226 | |
| 227 | if (ir->pcidev[device_num] == 0) { |
| 228 | printk(BIOS_WARNING, |
| 229 | "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", |
| 230 | device_num); |
| 231 | continue; |
| 232 | } |
| 233 | |
| 234 | /* Find the PIRQ that is attached to the INT_PIN this device uses */ |
| 235 | pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; |
| 236 | |
| 237 | /* Get the INT_LINE this device/function will use */ |
| 238 | int_line = ir->pic[pirq]; |
| 239 | |
| 240 | if (int_line != PIRQ_PIC_IRQDISABLE) { |
| 241 | /* Set this IRQ to level triggered since it is used by a PCI device */ |
| 242 | i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); |
| 243 | /* Set the Interrupt Line register in PCI config space */ |
| 244 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 245 | } else { |
| 246 | /* Set the Interrupt line register as "unknown or unused" */ |
| 247 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, |
| 248 | PIRQ_PIC_UNKNOWN_UNUSED); |
| 249 | } |
| 250 | |
| 251 | printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", |
| 252 | original_int_pin, pin_to_str(original_int_pin)); |
| 253 | if (parent_bdf != current_bdf) |
| 254 | printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", |
| 255 | new_int_pin, pin_to_str(new_int_pin)); |
| 256 | printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" |
| 257 | "\tINT_LINE\t: 0x%X (IRQ %d)\n", |
| 258 | 'A' + pirq, int_line, int_line); |
| 259 | } |
| 260 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); |
| 261 | } |
| 262 | |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 263 | static void sc_pirq_init(struct device *dev) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 264 | { |
| 265 | int i, j; |
| 266 | int pirq; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 267 | u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); |
| 268 | u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20); |
| 269 | u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 270 | const struct baytrail_irq_route *ir = &global_baytrail_irq_route; |
| 271 | |
| 272 | /* Set up the PIRQ PIC routing based on static config. */ |
| 273 | printk(BIOS_SPEW, "Start writing IRQ assignments\n" |
Elyes HAOUAS | 03b040b | 2016-08-25 21:11:45 +0200 | [diff] [blame] | 274 | "PIRQ\tA\tB\tC\tD\tE\tF\tG\tH\n" |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 275 | "IRQ "); |
| 276 | for (i = 0; i < NUM_PIRQS; i++) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 277 | write8(pr_base + i, ir->pic[i]); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 278 | printk(BIOS_SPEW, "\t%d", ir->pic[i]); |
| 279 | } |
| 280 | printk(BIOS_SPEW, "\n\n"); |
| 281 | |
| 282 | /* Set up the per device PIRQ routing based on static config. */ |
| 283 | printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n" |
| 284 | "Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n"); |
| 285 | for (i = 0; i < NUM_OF_PCI_DEVS; i++) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 286 | write16(ir_base + i, ir->pcidev[i]); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 287 | |
| 288 | /* If the entry is more than just 0, print it out */ |
Elyes HAOUAS | 4a83f1c | 2016-08-25 21:07:59 +0200 | [diff] [blame] | 289 | if (ir->pcidev[i]) { |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 290 | printk(BIOS_SPEW, " %d: ", i); |
| 291 | for (j = 0; j < 4; j++) { |
| 292 | pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; |
| 293 | printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]); |
| 294 | } |
| 295 | printk(BIOS_SPEW, "\n"); |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | /* Route SCI to IRQ9 */ |
| 300 | write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); |
| 301 | printk(BIOS_SPEW, "Finished writing IRQ assignments\n"); |
| 302 | |
| 303 | /* Write IRQ assignments to PCI config space */ |
| 304 | write_pci_config_irqs(); |
| 305 | } |
| 306 | |
| 307 | static inline int io_range_in_default(int base, int size) |
| 308 | { |
| 309 | /* Does it start above the range? */ |
| 310 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 311 | return 0; |
| 312 | |
| 313 | /* Is it entirely contained? */ |
| 314 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 315 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 316 | return 1; |
| 317 | |
| 318 | /* This will return not in range for partial overlaps. */ |
| 319 | return 0; |
| 320 | } |
| 321 | |
| 322 | /* |
| 323 | * Note: this function assumes there is no overlap with the default LPC device's |
| 324 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 325 | */ |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 326 | static void sc_add_io_resource(struct device *dev, int base, int size, int index) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 327 | { |
| 328 | struct resource *res; |
| 329 | |
| 330 | if (io_range_in_default(base, size)) |
| 331 | return; |
| 332 | |
| 333 | res = new_resource(dev, index); |
| 334 | res->base = base; |
| 335 | res->size = size; |
| 336 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | |
| 337 | IORESOURCE_FIXED; |
| 338 | } |
| 339 | |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 340 | static void sc_add_io_resources(struct device *dev) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 341 | { |
| 342 | struct resource *res; |
| 343 | u8 io_index = 0; |
| 344 | |
| 345 | /* |
| 346 | * Add the default claimed IO range for the LPC device |
| 347 | * and mark it as subtractive decode. |
| 348 | */ |
| 349 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 350 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 351 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 352 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 353 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 354 | |
| 355 | /* GPIO */ |
| 356 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); |
| 357 | |
| 358 | /* ACPI */ |
| 359 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); |
| 360 | } |
| 361 | |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 362 | static void sc_read_resources(struct device *dev) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 363 | { |
| 364 | /* Get the normal PCI resources of this device. */ |
| 365 | pci_dev_read_resources(dev); |
| 366 | |
| 367 | /* Add non-standard MMIO resources. */ |
| 368 | sc_add_mmio_resources(dev); |
| 369 | |
| 370 | /* Add IO resources. */ |
| 371 | sc_add_io_resources(dev); |
| 372 | } |
| 373 | |
| 374 | static void enable_hpet(void) |
| 375 | { |
| 376 | } |
| 377 | |
| 378 | static void sc_init(struct device *dev) |
| 379 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 380 | u8 *ibase; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 381 | |
| 382 | printk(BIOS_DEBUG, "soc: southcluster_init\n"); |
| 383 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 384 | ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 385 | |
| 386 | write8(ibase + ILB_MC, 0); |
| 387 | |
| 388 | /* Set the value for PCI command register. */ |
| 389 | pci_write_config16(dev, PCI_COMMAND, |
| 390 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 391 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); |
| 392 | |
| 393 | /* IO APIC initialization. */ |
| 394 | sc_enable_ioapic(dev); |
| 395 | |
| 396 | sc_enable_serial_irqs(dev); |
| 397 | |
| 398 | /* Setup the PIRQ. */ |
| 399 | sc_pirq_init(dev); |
| 400 | |
| 401 | /* Initialize the High Precision Event Timers, if present. */ |
| 402 | enable_hpet(); |
| 403 | |
| 404 | /* Initialize ISA DMA. */ |
| 405 | isa_dma_init(); |
| 406 | |
| 407 | setup_i8259(); |
| 408 | |
| 409 | setup_i8254(); |
| 410 | } |
| 411 | |
| 412 | /* |
| 413 | * Common code for the south cluster devices. |
| 414 | */ |
| 415 | |
| 416 | /* Set bit in function disable register to hide this device. */ |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 417 | static void sc_disable_devfn(struct device *dev) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 418 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 419 | u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); |
| 420 | u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 421 | uint32_t fd_mask = 0; |
| 422 | uint32_t fd2_mask = 0; |
| 423 | |
| 424 | #define SET_DIS_MASK(name_) \ |
| 425 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 426 | fd_mask |= name_ ## _DIS |
| 427 | #define SET_DIS_MASK2(name_) \ |
| 428 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ |
| 429 | fd2_mask |= name_ ## _DIS |
| 430 | |
| 431 | switch (dev->path.pci.devfn) { |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 432 | SET_DIS_MASK(LPE); |
| 433 | break; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 434 | SET_DIS_MASK(TXE); |
| 435 | break; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 436 | SET_DIS_MASK(PCIE_PORT1); |
| 437 | break; |
| 438 | SET_DIS_MASK(PCIE_PORT2); |
| 439 | break; |
| 440 | SET_DIS_MASK(PCIE_PORT3); |
| 441 | break; |
| 442 | SET_DIS_MASK(PCIE_PORT4); |
| 443 | break; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 444 | SET_DIS_MASK2(SMBUS); |
| 445 | break; |
| 446 | SET_DIS_MASK(OTG); |
| 447 | /* Disable OTG PHY when OTG is not available. */ |
| 448 | fd2_mask |= OTG_SS_PHY_DIS; |
| 449 | break; |
| 450 | } |
| 451 | |
| 452 | if (fd_mask != 0) { |
| 453 | write32(func_dis, read32(func_dis) | fd_mask); |
| 454 | /* Ensure posted write hits. */ |
| 455 | read32(func_dis); |
| 456 | } |
| 457 | |
| 458 | if (fd2_mask != 0) { |
| 459 | write32(func_dis2, read32(func_dis2) | fd2_mask); |
| 460 | /* Ensure posted write hits. */ |
| 461 | read32(func_dis2); |
| 462 | } |
| 463 | } |
| 464 | |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 465 | static inline void set_d3hot_bits(struct device *dev, int offset) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 466 | { |
| 467 | uint32_t reg8; |
| 468 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 469 | reg8 = pci_read_config8(dev, offset + 4); |
| 470 | reg8 |= 0x3; |
| 471 | pci_write_config8(dev, offset + 4, reg8); |
| 472 | } |
| 473 | |
| 474 | /* Parts of the audio subsystem are powered by the HDA device. Therefore, one |
| 475 | * cannot put HDA into D3Hot. Instead perform this workaround to make some of |
| 476 | * the audio paths work for LPE audio. */ |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 477 | static void hda_work_around(struct device *dev) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 478 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 479 | u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 480 | |
| 481 | /* Need to set magic register 0x43 to 0xd7 in config space. */ |
| 482 | pci_write_config8(dev, 0x43, 0xd7); |
| 483 | |
| 484 | /* Need to set bit 0 of GCTL to take the device out of reset. However, |
| 485 | * that requires setting up the 64-bit BAR. */ |
| 486 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); |
| 487 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); |
| 488 | pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
| 489 | write32(gctl, read32(gctl) | 0x1); |
| 490 | pci_write_config8(dev, PCI_COMMAND, 0); |
| 491 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 492 | } |
| 493 | |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 494 | static int place_device_in_d3hot(struct device *dev) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 495 | { |
| 496 | unsigned offset; |
| 497 | |
| 498 | /* Parts of the HDA block are used for LPE audio as well. |
| 499 | * Therefore assume the HDA will never be put into D3Hot. */ |
| 500 | if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { |
| 501 | hda_work_around(dev); |
| 502 | return 0; |
| 503 | } |
| 504 | |
| 505 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 506 | |
| 507 | if (offset != 0) { |
| 508 | set_d3hot_bits(dev, offset); |
| 509 | return 0; |
| 510 | } |
| 511 | |
| 512 | /* For some reason some of the devices don't have the capability |
| 513 | * pointer set correctly. Work around this by hard coding the offset. */ |
| 514 | #define DEV_CASE(name_) \ |
| 515 | case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) |
| 516 | |
| 517 | switch (dev->path.pci.devfn) { |
| 518 | DEV_CASE(MIPI): |
| 519 | DEV_CASE(SDIO): |
| 520 | DEV_CASE(EMMC): |
| 521 | DEV_CASE(SD): |
| 522 | DEV_CASE(MMC45): |
| 523 | DEV_CASE(LPE): |
| 524 | DEV_CASE(SIO_DMA1): |
| 525 | DEV_CASE(I2C1): |
| 526 | DEV_CASE(I2C2): |
| 527 | DEV_CASE(I2C3): |
| 528 | DEV_CASE(I2C4): |
| 529 | DEV_CASE(I2C5): |
| 530 | DEV_CASE(I2C6): |
| 531 | DEV_CASE(I2C7): |
| 532 | DEV_CASE(SIO_DMA2): |
| 533 | DEV_CASE(PWM1): |
| 534 | DEV_CASE(PWM2): |
| 535 | DEV_CASE(HSUART1): |
| 536 | DEV_CASE(HSUART2): |
| 537 | DEV_CASE(SPI): |
| 538 | DEV_CASE(OTG): |
| 539 | offset = 0x80; |
| 540 | break; |
| 541 | DEV_CASE(SATA): |
| 542 | DEV_CASE(XHCI): |
| 543 | DEV_CASE(EHCI): |
| 544 | offset = 0x70; |
| 545 | break; |
| 546 | DEV_CASE(HDA): |
| 547 | DEV_CASE(SMBUS): |
| 548 | offset = 0x50; |
| 549 | break; |
| 550 | DEV_CASE(TXE): |
| 551 | /* TXE cannot be placed in D3Hot. */ |
| 552 | return 0; |
| 553 | break; |
| 554 | DEV_CASE(PCIE_PORT1): |
| 555 | DEV_CASE(PCIE_PORT2): |
| 556 | DEV_CASE(PCIE_PORT3): |
| 557 | DEV_CASE(PCIE_PORT4): |
| 558 | offset = 0xa0; |
| 559 | break; |
| 560 | } |
| 561 | |
| 562 | if (offset != 0) { |
| 563 | set_d3hot_bits(dev, offset); |
| 564 | return 0; |
| 565 | } |
| 566 | |
| 567 | return -1; |
| 568 | } |
| 569 | |
| 570 | /* Common PCI device function disable. */ |
Elyes HAOUAS | 509edac | 2018-05-27 17:48:32 +0200 | [diff] [blame] | 571 | void southcluster_enable_dev(struct device *dev) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 572 | { |
| 573 | uint32_t reg32; |
| 574 | |
| 575 | if (!dev->enabled) { |
| 576 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 577 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 578 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 579 | dev_path(dev), slot, func); |
| 580 | |
| 581 | /* Ensure memory, io, and bus master are all disabled */ |
| 582 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 583 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 584 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 585 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 586 | |
| 587 | /* Place device in D3Hot */ |
| 588 | if (place_device_in_d3hot(dev) < 0) { |
| 589 | printk(BIOS_WARNING, |
| 590 | "Could not place %02x.%01x into D3Hot. " |
| 591 | "Keeping device visible.\n", slot, func); |
| 592 | return; |
| 593 | } |
| 594 | /* Disable this device if possible */ |
| 595 | sc_disable_devfn(dev); |
| 596 | } else { |
| 597 | /* Enable SERR */ |
| 598 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 599 | reg32 |= PCI_COMMAND_SERR; |
| 600 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 601 | } |
| 602 | } |
| 603 | |
| 604 | static struct device_operations device_ops = { |
| 605 | .read_resources = sc_read_resources, |
| 606 | .set_resources = pci_dev_set_resources, |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 607 | .acpi_inject_dsdt_generator = southcluster_inject_dsdt, |
| 608 | .write_acpi_tables = southcluster_write_acpi_tables, |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 609 | .enable_resources = NULL, |
| 610 | .init = sc_init, |
| 611 | .enable = southcluster_enable_dev, |
Kyösti Mälkki | d0e212c | 2015-02-26 20:47:47 +0200 | [diff] [blame] | 612 | .scan_bus = scan_lpc_bus, |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 613 | .ops_pci = &soc_pci_ops, |
| 614 | }; |
| 615 | |
| 616 | static const struct pci_driver southcluster __pci_driver = { |
| 617 | .ops = &device_ops, |
| 618 | .vendor = PCI_VENDOR_ID_INTEL, |
| 619 | .device = LPC_DEVID, |
| 620 | }; |