Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stddef.h> |
| 17 | #include <stdint.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 18 | #include <arch/cbfs.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 19 | #include <arch/early_variables.h> |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 20 | #include <bootblock_common.h> |
Julius Werner | b04cc6b | 2017-03-17 14:14:14 -0700 | [diff] [blame] | 21 | #include <bootmode.h> |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 22 | #include <cbmem.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 23 | #include <console/console.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 24 | #include <cpu/x86/mtrr.h> |
| 25 | #include <elog.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 26 | #include <program_loading.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 27 | #include <romstage_handoff.h> |
Aaron Durbin | bd74a4b | 2015-03-06 23:17:33 -0600 | [diff] [blame] | 28 | #include <stage_cache.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 29 | #include <timestamp.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 30 | #include <soc/me.h> |
| 31 | #include <soc/pei_data.h> |
| 32 | #include <soc/pm.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 33 | #include <soc/romstage.h> |
| 34 | #include <soc/spi.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 35 | |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 36 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
| 37 | |
| 38 | /* platform_enter_postcar() determines the stack to use after |
| 39 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 40 | * and continues execution in postcar stage. */ |
| 41 | static void platform_enter_postcar(void) |
| 42 | { |
| 43 | struct postcar_frame pcf; |
| 44 | uintptr_t top_of_ram; |
| 45 | |
| 46 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 47 | die("Unable to initialize postcar frame.\n"); |
| 48 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 4c7eee2 | 2019-02-10 19:35:41 +0100 | [diff] [blame] | 49 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 50 | |
| 51 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 52 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 53 | |
| 54 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 55 | * above top of the ram. This satisfies MTRR alignment requirement |
| 56 | * with different TSEG size configurations. |
| 57 | */ |
| 58 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
| 59 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, |
| 60 | MTRR_TYPE_WRBACK); |
| 61 | |
| 62 | run_postcar_phase(&pcf); |
| 63 | } |
| 64 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 65 | /* Entry from cache-as-ram.inc. */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 66 | static void romstage_main(uint64_t tsc, uint32_t bist) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 67 | { |
| 68 | struct romstage_params rp = { |
| 69 | .bist = bist, |
| 70 | .pei_data = NULL, |
| 71 | }; |
| 72 | |
| 73 | post_code(0x30); |
| 74 | |
| 75 | /* Save initial timestamp from bootblock. */ |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 76 | timestamp_init(tsc); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 77 | |
| 78 | /* Save romstage begin */ |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 79 | timestamp_add_now(TS_START_ROMSTAGE); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 80 | |
| 81 | /* System Agent Early Initialization */ |
| 82 | systemagent_early_init(); |
| 83 | |
| 84 | /* PCH Early Initialization */ |
| 85 | pch_early_init(); |
| 86 | |
Wenkai Du | 1006b10 | 2014-11-05 21:10:57 -0800 | [diff] [blame] | 87 | /* Call into mainboard pre console init. Needed to enable serial port |
| 88 | on IT8772 */ |
| 89 | mainboard_pre_console_init(); |
| 90 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 91 | /* Start console drivers */ |
| 92 | console_init(); |
| 93 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 94 | /* Get power state */ |
| 95 | rp.power_state = fill_power_state(); |
| 96 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 97 | /* Print useful platform information */ |
| 98 | report_platform_info(); |
| 99 | |
| 100 | /* Set CPU frequency to maximum */ |
| 101 | set_max_freq(); |
| 102 | |
| 103 | /* Call into mainboard. */ |
| 104 | mainboard_romstage_entry(&rp); |
| 105 | |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 106 | platform_enter_postcar(); |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 107 | } |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 108 | |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 109 | /* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, |
| 110 | * keeping changes in cache_as_ram.S easy to manage. |
| 111 | */ |
| 112 | asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) |
| 113 | { |
| 114 | romstage_main(base_timestamp, bist); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 115 | } |
| 116 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 117 | /* Entry from the mainboard. */ |
| 118 | void romstage_common(struct romstage_params *params) |
| 119 | { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 120 | post_code(0x32); |
| 121 | |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 122 | timestamp_add_now(TS_BEFORE_INITRAM); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 123 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 124 | params->pei_data->boot_mode = params->power_state->prev_sleep_state; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 125 | |
Martin Roth | e6ff159 | 2017-06-24 21:34:29 -0600 | [diff] [blame] | 126 | #if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 127 | if (params->power_state->prev_sleep_state != ACPI_S3) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 128 | boot_count_increment(); |
| 129 | #endif |
| 130 | |
| 131 | /* Print ME state before MRC */ |
| 132 | intel_me_status(); |
| 133 | |
Duncan Laurie | a7d8ea8 | 2014-08-26 13:49:24 -0700 | [diff] [blame] | 134 | /* Save ME HSIO version */ |
| 135 | intel_me_hsio_version(¶ms->power_state->hsio_version, |
| 136 | ¶ms->power_state->hsio_checksum); |
| 137 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 138 | /* Initialize RAM */ |
| 139 | raminit(params->pei_data); |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 140 | |
| 141 | timestamp_add_now(TS_AFTER_INITRAM); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 142 | |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 143 | romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 146 | void __weak mainboard_pre_console_init(void) {} |