Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Duncan Laurie | e86ac7e | 2014-10-07 15:19:54 -0700 | [diff] [blame] | 16 | #include <arch/acpi.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 17 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 19 | #include <bootmode.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 20 | #include <console/console.h> |
| 21 | #include <delay.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <stdlib.h> |
| 26 | #include <string.h> |
| 27 | #include <reg_script.h> |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 28 | #include <cbmem.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 29 | #include <drivers/intel/gma/i915_reg.h> |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 30 | #include <drivers/intel/gma/opregion.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 31 | #include <soc/cpu.h> |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 32 | #include <soc/nvs.h> |
Duncan Laurie | 1e6b591 | 2015-01-30 16:33:43 -0800 | [diff] [blame] | 33 | #include <soc/pm.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 34 | #include <soc/ramstage.h> |
| 35 | #include <soc/systemagent.h> |
| 36 | #include <soc/intel/broadwell/chip.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 37 | #include <security/vboot/vbnv.h> |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 38 | #include <soc/igd.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 39 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 40 | #define GT_RETRY 1000 |
| 41 | enum { |
| 42 | GT_CDCLK_DEFAULT = 0, |
| 43 | GT_CDCLK_337, |
| 44 | GT_CDCLK_450, |
| 45 | GT_CDCLK_540, |
| 46 | GT_CDCLK_675, |
| 47 | }; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 48 | |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 49 | static u32 reg_em4; |
| 50 | static u32 reg_em5; |
| 51 | |
| 52 | u32 igd_get_reg_em4(void) { return reg_em4; } |
| 53 | u32 igd_get_reg_em5(void) { return reg_em5; } |
| 54 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 55 | struct reg_script haswell_early_init_script[] = { |
| 56 | /* Enable Force Wake */ |
| 57 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), |
| 58 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 59 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 60 | |
| 61 | /* Enable Counters */ |
| 62 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), |
| 63 | |
| 64 | /* GFXPAUSE settings */ |
| 65 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020), |
| 66 | |
| 67 | /* ECO Settings */ |
| 68 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000), |
| 69 | |
| 70 | /* Enable DOP Clock Gating */ |
| 71 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd), |
| 72 | |
| 73 | /* Enable Unit Level Clock Gating */ |
| 74 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080), |
| 75 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000), |
| 76 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000), |
| 77 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001), |
| 78 | |
| 79 | /* |
| 80 | * RC6 Settings |
| 81 | */ |
| 82 | |
| 83 | /* Wake Rate Limits */ |
| 84 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa090, 0x00000000), |
| 85 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa098, 0x03e80000), |
| 86 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa09c, 0x00280000), |
| 87 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0a8, 0x0001e848), |
| 88 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0ac, 0x00000019), |
| 89 | |
| 90 | /* Render/Video/Blitter Idle Max Count */ |
| 91 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a), |
| 92 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a), |
| 93 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a), |
| 94 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a), |
| 95 | |
| 96 | /* RC Sleep / RCx Thresholds */ |
| 97 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b0, 0x00000000), |
| 98 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b4, 0x000003e8), |
| 99 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b8, 0x0000c350), |
| 100 | |
| 101 | /* RP Settings */ |
| 102 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa010, 0x000f4240), |
| 103 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa014, 0x12060000), |
| 104 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa02c, 0x0000e808), |
| 105 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa030, 0x0003bd08), |
| 106 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa068, 0x000101d0), |
| 107 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa06c, 0x00055730), |
| 108 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a), |
| 109 | |
| 110 | /* RP Control */ |
| 111 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92), |
| 112 | |
| 113 | /* HW RC6 Control */ |
| 114 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x88040000), |
| 115 | |
| 116 | /* Video Frequency Request */ |
| 117 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000), |
| 118 | |
| 119 | /* Set RC6 VIDs */ |
| 120 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 121 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), |
| 122 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), |
| 123 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 124 | |
| 125 | /* Enable PM Interrupts */ |
| 126 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), |
| 127 | |
| 128 | /* Enable RC6 in idle */ |
| 129 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000), |
| 130 | |
| 131 | REG_SCRIPT_END |
| 132 | }; |
| 133 | |
| 134 | static const struct reg_script haswell_late_init_script[] = { |
| 135 | /* Lock settings */ |
| 136 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)), |
| 137 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a004, (1 << 4)), |
| 138 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a080, (1 << 2)), |
| 139 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)), |
| 140 | |
| 141 | /* Disable Force Wake */ |
| 142 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 143 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 144 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001), |
| 145 | |
| 146 | /* Enable power well for DP and Audio */ |
| 147 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), |
| 148 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, |
| 149 | (1 << 30), (1 << 30), GT_RETRY), |
| 150 | |
| 151 | REG_SCRIPT_END |
| 152 | }; |
| 153 | |
| 154 | static const struct reg_script broadwell_early_init_script[] = { |
| 155 | /* Enable Force Wake */ |
| 156 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 157 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 158 | |
| 159 | /* Enable push bus metric control and shift */ |
| 160 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004), |
| 161 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff), |
| 162 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010), |
| 163 | |
Duncan Laurie | 84b9cf4 | 2014-07-31 10:46:57 -0700 | [diff] [blame] | 164 | /* GFXPAUSE settings (set based on stepping) */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 165 | |
| 166 | /* ECO Settings */ |
| 167 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000), |
| 168 | |
| 169 | /* Enable DOP Clock Gating */ |
| 170 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000000fd), |
| 171 | |
| 172 | /* Enable Unit Level Clock Gating */ |
| 173 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000000), |
| 174 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000), |
| 175 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000), |
| 176 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001), |
| 177 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a), |
| 178 | |
| 179 | /* Video Frequency Request */ |
| 180 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000), |
| 181 | |
Duncan Laurie | 84b9cf4 | 2014-07-31 10:46:57 -0700 | [diff] [blame] | 182 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138158, 0x00000009), |
| 183 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x13815c, 0x0000000d), |
| 184 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 185 | /* |
| 186 | * RC6 Settings |
| 187 | */ |
| 188 | |
| 189 | /* Wake Rate Limits */ |
| 190 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0a090, 0, 0), |
| 191 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a098, 0x03e80000), |
| 192 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a09c, 0x00280000), |
| 193 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0a8, 0x0001e848), |
| 194 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0ac, 0x00000019), |
| 195 | |
| 196 | /* Render/Video/Blitter Idle Max Count */ |
| 197 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a), |
| 198 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a), |
| 199 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a), |
| 200 | |
| 201 | /* RC Sleep / RCx Thresholds */ |
| 202 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b0, 0x00000000), |
| 203 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b8, 0x00000271), |
| 204 | |
| 205 | /* RP Settings */ |
| 206 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a010, 0x000f4240), |
| 207 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a014, 0x12060000), |
| 208 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a02c, 0x0000e808), |
| 209 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a030, 0x0003bd08), |
| 210 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a068, 0x000101d0), |
| 211 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a06c, 0x00055730), |
| 212 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a070, 0x0000000a), |
| 213 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a168, 0x00000006), |
| 214 | |
| 215 | /* RP Control */ |
| 216 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92), |
| 217 | |
| 218 | /* HW RC6 Control */ |
| 219 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000), |
| 220 | |
| 221 | /* Set RC6 VIDs */ |
| 222 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 223 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), |
| 224 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), |
| 225 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 226 | |
| 227 | /* Enable PM Interrupts */ |
| 228 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), |
| 229 | |
| 230 | /* Enable RC6 in idle */ |
| 231 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000), |
| 232 | |
| 233 | REG_SCRIPT_END |
| 234 | }; |
| 235 | |
| 236 | static const struct reg_script broadwell_late_init_script[] = { |
| 237 | /* Lock settings */ |
| 238 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)), |
| 239 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a000, (1 << 18)), |
| 240 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)), |
| 241 | |
| 242 | /* Disable Force Wake */ |
| 243 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 244 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 245 | |
| 246 | /* Enable power well for DP and Audio */ |
| 247 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), |
| 248 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, |
| 249 | (1 << 30), (1 << 30), GT_RETRY), |
| 250 | |
| 251 | REG_SCRIPT_END |
| 252 | }; |
| 253 | |
| 254 | u32 map_oprom_vendev(u32 vendev) |
| 255 | { |
| 256 | return SA_IGD_OPROM_VENDEV; |
| 257 | } |
| 258 | |
| 259 | static struct resource *gtt_res = NULL; |
| 260 | |
| 261 | static unsigned long gtt_read(unsigned long reg) |
| 262 | { |
| 263 | u32 val; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 264 | val = read32(res2mmio(gtt_res, reg, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 265 | return val; |
| 266 | |
| 267 | } |
| 268 | |
| 269 | static void gtt_write(unsigned long reg, unsigned long data) |
| 270 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 271 | write32(res2mmio(gtt_res, reg, 0), data); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) |
| 275 | { |
| 276 | u32 val = gtt_read(reg); |
| 277 | val &= andmask; |
| 278 | val |= ormask; |
| 279 | gtt_write(reg, val); |
| 280 | } |
| 281 | |
| 282 | static int gtt_poll(u32 reg, u32 mask, u32 value) |
| 283 | { |
Lee Leahy | 23602df | 2017-03-16 19:00:37 -0700 | [diff] [blame] | 284 | unsigned int try = GT_RETRY; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 285 | u32 data; |
| 286 | |
| 287 | while (try--) { |
| 288 | data = gtt_read(reg); |
| 289 | if ((data & mask) == value) |
| 290 | return 1; |
| 291 | udelay(10); |
| 292 | } |
| 293 | |
| 294 | printk(BIOS_ERR, "GT init timeout\n"); |
| 295 | return 0; |
| 296 | } |
| 297 | |
| 298 | static void igd_setup_panel(struct device *dev) |
| 299 | { |
| 300 | config_t *conf = dev->chip_info; |
| 301 | u32 reg32; |
| 302 | |
| 303 | /* Setup Digital Port Hotplug */ |
| 304 | reg32 = gtt_read(PCH_PORT_HOTPLUG); |
| 305 | if (!reg32) { |
| 306 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 307 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 308 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 309 | gtt_write(PCH_PORT_HOTPLUG, reg32); |
| 310 | } |
| 311 | |
| 312 | /* Setup Panel Power On Delays */ |
| 313 | reg32 = gtt_read(PCH_PP_ON_DELAYS); |
| 314 | if (!reg32) { |
| 315 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 316 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 317 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 318 | gtt_write(PCH_PP_ON_DELAYS, reg32); |
| 319 | } |
| 320 | |
| 321 | /* Setup Panel Power Off Delays */ |
| 322 | reg32 = gtt_read(PCH_PP_OFF_DELAYS); |
| 323 | if (!reg32) { |
| 324 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 325 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 326 | gtt_write(PCH_PP_OFF_DELAYS, reg32); |
| 327 | } |
| 328 | |
| 329 | /* Setup Panel Power Cycle Delay */ |
| 330 | if (conf->gpu_panel_power_cycle_delay) { |
| 331 | reg32 = gtt_read(PCH_PP_DIVISOR); |
| 332 | reg32 &= ~0xff; |
| 333 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 334 | gtt_write(PCH_PP_DIVISOR, reg32); |
| 335 | } |
| 336 | |
| 337 | /* Enable Backlight if needed */ |
| 338 | if (conf->gpu_cpu_backlight) { |
| 339 | gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); |
| 340 | gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); |
| 341 | } |
| 342 | if (conf->gpu_pch_backlight) { |
| 343 | gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); |
| 344 | gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); |
| 345 | } |
| 346 | } |
| 347 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 348 | static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc, |
| 349 | struct device *const dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 350 | { |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 351 | const config_t *const conf = dev->chip_info; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 352 | int cdclk = conf->cdclk; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 353 | |
| 354 | /* Check for ULX GT1 or GT2 */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 355 | const int devid = pci_read_config16(dev, PCI_DEVICE_ID); |
| 356 | const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 || |
| 357 | devid == IGD_HASWELL_ULX_GT2; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 358 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 359 | /* Check for fixed fused clock */ |
| 360 | if (gtt_read(0x42014) & 1 << 24) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 361 | cdclk = GT_CDCLK_450; |
| 362 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 363 | /* |
| 364 | * ULX defaults to 337MHz with possible override for 450MHz |
| 365 | * ULT is fixed at 450MHz |
| 366 | * others default to 540MHz with possible override for 450MHz |
| 367 | */ |
| 368 | if (gpu_is_ulx && cdclk <= GT_CDCLK_337) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 369 | cdclk = GT_CDCLK_337; |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 370 | else if (gpu_is_ulx || cpu_is_ult() || |
| 371 | cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 372 | cdclk = GT_CDCLK_450; |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 373 | else |
| 374 | cdclk = GT_CDCLK_540; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 375 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 376 | *cdsel = cdclk != GT_CDCLK_450; |
| 377 | *inform_pc = gpu_is_ulx; |
| 378 | return cdclk; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 379 | } |
| 380 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 381 | static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc, |
| 382 | struct device *const dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 383 | { |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 384 | static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 }; |
| 385 | const config_t *const conf = dev->chip_info; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 386 | int cdclk = conf->cdclk; |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 387 | |
| 388 | /* Check for ULX */ |
| 389 | const int devid = pci_read_config16(dev, PCI_DEVICE_ID); |
| 390 | const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 391 | |
| 392 | /* Inform power controller of upcoming frequency change */ |
| 393 | gtt_write(0x138128, 0); |
| 394 | gtt_write(0x13812c, 0); |
| 395 | gtt_write(0x138124, 0x80000018); |
| 396 | |
| 397 | /* Poll GT driver mailbox for run/busy clear */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 398 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { |
| 399 | *inform_pc = 1; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 400 | } else { |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 401 | cdclk = GT_CDCLK_450; |
| 402 | *inform_pc = 0; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 403 | } |
| 404 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 405 | /* Check for fixed fused clock */ |
| 406 | if (gtt_read(0x42014) & 1 << 24) |
| 407 | cdclk = GT_CDCLK_450; |
| 408 | |
| 409 | /* |
| 410 | * ULX defaults to 450MHz with possible override up to 540MHz |
| 411 | * ULT defaults to 540MHz with possible override up to 675MHz |
| 412 | * others default to 675MHz with possible override for lower freqs |
| 413 | */ |
| 414 | if (cdclk == GT_CDCLK_337) |
| 415 | cdclk = GT_CDCLK_337; |
| 416 | else if (cdclk == GT_CDCLK_450 || |
| 417 | (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT)) |
| 418 | cdclk = GT_CDCLK_450; |
| 419 | else if (cdclk == GT_CDCLK_540 || gpu_is_ulx || |
| 420 | (cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT)) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 421 | cdclk = GT_CDCLK_540; |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 422 | else |
| 423 | cdclk = GT_CDCLK_675; |
| 424 | |
| 425 | *cdsel = cdsel_by_cdclk[cdclk]; |
| 426 | return cdclk; |
| 427 | } |
| 428 | |
| 429 | static void igd_cdclk_init(struct device *dev, const int is_broadwell) |
| 430 | { |
| 431 | u32 dpdiv, cdsel, cdval; |
| 432 | int cdclk, inform_pc; |
| 433 | |
| 434 | if (is_broadwell) |
| 435 | cdclk = igd_get_cdclk_broadwell(&cdsel, &inform_pc, dev); |
| 436 | else |
| 437 | cdclk = igd_get_cdclk_haswell(&cdsel, &inform_pc, dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 438 | |
| 439 | /* Set variables based on CD Clock setting */ |
| 440 | switch (cdclk) { |
| 441 | case GT_CDCLK_337: |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 442 | cdval = 337; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 443 | dpdiv = 169; |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 444 | reg_em4 = 16; |
| 445 | reg_em5 = 225; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 446 | break; |
| 447 | case GT_CDCLK_450: |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 448 | cdval = 449; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 449 | dpdiv = 225; |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 450 | reg_em4 = 4; |
| 451 | reg_em5 = 75; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 452 | break; |
| 453 | case GT_CDCLK_540: |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 454 | cdval = 539; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 455 | dpdiv = 270; |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 456 | reg_em4 = 4; |
| 457 | reg_em5 = 90; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 458 | break; |
| 459 | case GT_CDCLK_675: |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 460 | cdval = 674; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 461 | dpdiv = 338; |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 462 | reg_em4 = 8; |
| 463 | reg_em5 = 225; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 464 | default: |
| 465 | return; |
| 466 | } |
| 467 | |
| 468 | /* Set LPCLL_CTL CD Clock Frequency Select */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 469 | gtt_rmw(0x130040, 0xf3ffffff, cdsel << 26); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 470 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 471 | if (inform_pc) { |
| 472 | /* Inform power controller of selected frequency */ |
| 473 | gtt_write(0x138128, cdsel); |
| 474 | gtt_write(0x13812c, 0); |
| 475 | gtt_write(0x138124, 0x80000017); |
| 476 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 477 | |
| 478 | /* Program CD Clock Frequency */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 479 | gtt_rmw(0x46200, 0xfffffc00, cdval); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 480 | |
| 481 | /* Set CPU DP AUX 2X bit clock dividers */ |
| 482 | gtt_rmw(0x64010, 0xfffff800, dpdiv); |
| 483 | gtt_rmw(0x64810, 0xfffff800, dpdiv); |
| 484 | } |
| 485 | |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 486 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 487 | { |
| 488 | const global_nvs_t *gnvs_ptr = gnvs; |
| 489 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 490 | } |
| 491 | |
| 492 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 493 | { |
| 494 | global_nvs_t *gnvs_ptr = gnvs; |
| 495 | if (gnvs_ptr) |
| 496 | gnvs_ptr->aslb = aslb; |
| 497 | } |
| 498 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 499 | static void igd_init(struct device *dev) |
| 500 | { |
| 501 | int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); |
| 502 | u32 rp1_gfx_freq; |
| 503 | |
| 504 | /* IGD needs to be Bus Master */ |
| 505 | u32 reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 506 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 507 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 508 | |
| 509 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 510 | if (!gtt_res || !gtt_res->base) |
| 511 | return; |
| 512 | |
| 513 | /* Wait for any configured pre-graphics delay */ |
Kyösti Mälkki | 1ec23c9 | 2015-05-29 06:18:18 +0300 | [diff] [blame] | 514 | if (!acpi_is_wakeup_s3()) { |
Duncan Laurie | b8a7b71 | 2014-11-10 13:00:27 -0800 | [diff] [blame] | 515 | #if IS_ENABLED(CONFIG_CHROMEOS) |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 516 | if (display_init_required() || vboot_wants_oprom()) |
Duncan Laurie | 1e6b591 | 2015-01-30 16:33:43 -0800 | [diff] [blame] | 517 | mdelay(CONFIG_PRE_GRAPHICS_DELAY); |
Duncan Laurie | b8a7b71 | 2014-11-10 13:00:27 -0800 | [diff] [blame] | 518 | #else |
Duncan Laurie | 1e6b591 | 2015-01-30 16:33:43 -0800 | [diff] [blame] | 519 | mdelay(CONFIG_PRE_GRAPHICS_DELAY); |
Duncan Laurie | b8a7b71 | 2014-11-10 13:00:27 -0800 | [diff] [blame] | 520 | #endif |
Duncan Laurie | 1e6b591 | 2015-01-30 16:33:43 -0800 | [diff] [blame] | 521 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 522 | |
| 523 | /* Early init steps */ |
| 524 | if (is_broadwell) { |
| 525 | reg_script_run_on_dev(dev, broadwell_early_init_script); |
Duncan Laurie | 84b9cf4 | 2014-07-31 10:46:57 -0700 | [diff] [blame] | 526 | |
| 527 | /* Set GFXPAUSE based on stepping */ |
| 528 | if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) && |
| 529 | systemagent_revision() <= 9) { |
| 530 | gtt_write(0xa000, 0x300ff); |
| 531 | } else { |
| 532 | gtt_write(0xa000, 0x30020); |
| 533 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 534 | } else { |
| 535 | reg_script_run_on_dev(dev, haswell_early_init_script); |
| 536 | } |
| 537 | |
| 538 | /* Set RP1 graphics frequency */ |
| 539 | rp1_gfx_freq = (MCHBAR32(0x5998) >> 8) & 0xff; |
| 540 | gtt_write(0xa008, rp1_gfx_freq << 24); |
| 541 | |
| 542 | /* Post VBIOS panel setup */ |
| 543 | igd_setup_panel(dev); |
| 544 | |
| 545 | /* Initialize PCI device, load/execute BIOS Option ROM */ |
| 546 | pci_dev_init(dev); |
| 547 | |
| 548 | /* Late init steps */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 549 | igd_cdclk_init(dev, is_broadwell); |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 550 | if (is_broadwell) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 551 | reg_script_run_on_dev(dev, broadwell_late_init_script); |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 552 | else |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 553 | reg_script_run_on_dev(dev, haswell_late_init_script); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 554 | |
Duncan Laurie | 49efaf2 | 2014-10-09 16:13:24 -0700 | [diff] [blame] | 555 | if (gfx_get_init_done()) { |
| 556 | /* |
| 557 | * Work around VBIOS issue that is not clearing first 64 |
| 558 | * bytes of the framebuffer during VBE mode set. |
| 559 | */ |
| 560 | struct resource *fb = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 561 | memset((void *)((u32)fb->base), 0, 64); |
| 562 | } |
| 563 | |
Kyösti Mälkki | 1ec23c9 | 2015-05-29 06:18:18 +0300 | [diff] [blame] | 564 | if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) { |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 565 | /* |
| 566 | * Enable DDI-A if the Option ROM did not execute: |
| 567 | * |
| 568 | * bit 0: Display detected (RO) |
| 569 | * bit 4: DDI A supports 4 lanes and DDI E is not used |
| 570 | * bit 7: DDI buffer is idle |
| 571 | */ |
| 572 | gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | |
| 573 | DDI_INIT_DISPLAY_DETECTED); |
| 574 | } |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 575 | |
| 576 | intel_gma_restore_opregion(); |
| 577 | } |
| 578 | |
| 579 | static unsigned long |
| 580 | gma_write_acpi_tables(struct device *const dev, unsigned long current, |
| 581 | struct acpi_rsdp *const rsdp) |
| 582 | { |
| 583 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
| 584 | global_nvs_t *gnvs; |
| 585 | |
| 586 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
| 587 | return current; |
| 588 | |
| 589 | current += sizeof(igd_opregion_t); |
| 590 | |
| 591 | /* GNVS has been already set up */ |
| 592 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 593 | if (gnvs) { |
| 594 | /* IGD OpRegion Base Address */ |
| 595 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
| 596 | } else { |
| 597 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
| 598 | } |
| 599 | |
| 600 | current = acpi_align_current(current); |
| 601 | return current; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 602 | } |
| 603 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 604 | static struct device_operations igd_ops = { |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 605 | .read_resources = &pci_dev_read_resources, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 606 | .set_resources = &pci_dev_set_resources, |
| 607 | .enable_resources = &pci_dev_enable_resources, |
| 608 | .init = &igd_init, |
| 609 | .ops_pci = &broadwell_pci_ops, |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 610 | .write_acpi_tables = gma_write_acpi_tables, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 611 | }; |
| 612 | |
| 613 | static const unsigned short pci_device_ids[] = { |
| 614 | IGD_HASWELL_ULT_GT1, |
| 615 | IGD_HASWELL_ULT_GT2, |
| 616 | IGD_HASWELL_ULT_GT3, |
| 617 | IGD_BROADWELL_U_GT1, |
| 618 | IGD_BROADWELL_U_GT2, |
| 619 | IGD_BROADWELL_U_GT3_15W, |
| 620 | IGD_BROADWELL_U_GT3_28W, |
| 621 | IGD_BROADWELL_Y_GT2, |
| 622 | IGD_BROADWELL_H_GT2, |
| 623 | IGD_BROADWELL_H_GT3, |
| 624 | 0, |
| 625 | }; |
| 626 | |
| 627 | static const struct pci_driver igd_driver __pci_driver = { |
| 628 | .ops = &igd_ops, |
| 629 | .vendor = PCI_VENDOR_ID_INTEL, |
| 630 | .devices = pci_device_ids, |
| 631 | }; |