Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 4 | * Copyright (C) 2016 Intel Corporation.. |
| 5 | * Copyright (C) 2017 Advanced Micro Devices |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
Marshall Dawson | a5f225f | 2017-08-18 10:07:07 -0600 | [diff] [blame] | 18 | #include <assert.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 19 | #include <console/console.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 20 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 21 | #include <cpu/amd/msr.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 22 | #include <cpu/x86/mtrr.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 23 | #include <smp/node.h> |
| 24 | #include <bootblock_common.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 25 | #include <amdblocks/agesawrapper.h> |
| 26 | #include <amdblocks/agesawrapper_call.h> |
Marshall Dawson | f5e057c | 2017-10-12 16:10:14 -0600 | [diff] [blame] | 27 | #include <soc/pci_devs.h> |
Marshall Dawson | d85c4af | 2018-03-28 19:48:42 -0600 | [diff] [blame] | 28 | #include <soc/cpu.h> |
Marshall Dawson | f5e057c | 2017-10-12 16:10:14 -0600 | [diff] [blame] | 29 | #include <soc/northbridge.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 30 | #include <soc/southbridge.h> |
Marshall Dawson | f5e057c | 2017-10-12 16:10:14 -0600 | [diff] [blame] | 31 | #include <amdblocks/psp.h> |
Aaron Durbin | 51e4c1a | 2018-01-24 17:42:51 -0700 | [diff] [blame] | 32 | #include <timestamp.h> |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 33 | #include <halt.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 34 | |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 35 | #if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 |
| 36 | #error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" |
| 37 | #endif |
| 38 | #if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000 |
| 39 | #error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" |
| 40 | #endif |
| 41 | |
| 42 | /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 43 | static void amd_initmmio(void) |
| 44 | { |
| 45 | msr_t mmconf; |
| 46 | msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); |
| 47 | int mtrr; |
| 48 | |
| 49 | mmconf.hi = 0; |
| 50 | mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN |
| 51 | | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; |
| 52 | wrmsr(MMIO_CONF_BASE, mmconf); |
| 53 | |
| 54 | /* |
| 55 | * todo: AGESA currently writes variable MTRRs. Once that is |
| 56 | * corrected, un-hardcode this MTRR. |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 57 | * |
| 58 | * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs |
| 59 | * where all cores execute the path. Both cores within a compute |
| 60 | * unit share MTRRs. Programming core0 has the appearance of |
| 61 | * modifying core1 too. Using the pair again will create |
| 62 | * duplicate copies. |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 63 | */ |
Marshall Dawson | d85c4af | 2018-03-28 19:48:42 -0600 | [diff] [blame] | 64 | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 65 | set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
Marshall Dawson | c4be175 | 2018-05-07 09:59:10 -0600 | [diff] [blame] | 66 | |
| 67 | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP; |
| 68 | set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, |
| 69 | CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); |
| 70 | |
| 71 | mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM; |
| 72 | set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE, |
| 73 | CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 74 | } |
| 75 | |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 76 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 77 | { |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 78 | amd_initmmio(); |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 79 | /* |
| 80 | * Call lib/bootblock.c main with BSP, shortcut for APs |
| 81 | */ |
| 82 | if (!boot_cpu()) { |
| 83 | void (*ap_romstage_entry)(void) = |
| 84 | (void (*)(void))get_ap_entry_ptr(); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 85 | |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 86 | ap_romstage_entry(); /* execution does not return */ |
| 87 | halt(); |
| 88 | } |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 89 | |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 90 | /* TSC cannot be relied upon. Override the TSC value passed in. */ |
Julius Werner | 12574dd | 2018-05-15 17:48:30 -0700 | [diff] [blame] | 91 | bootblock_main_with_timestamp(timestamp_get(), NULL, 0); |
Richard Spiegel | 6d61db0 | 2018-04-04 10:35:21 -0700 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | void bootblock_soc_early_init(void) |
| 95 | { |
Richard Spiegel | 5401aa2 | 2018-09-11 11:36:38 -0700 | [diff] [blame] | 96 | /* |
| 97 | * This call (sb_reset_i2c_slaves) was originally early at |
| 98 | * bootblock_c_entry, but had to be moved here. There was an |
| 99 | * unexplained delay in the middle of the i2c transaction when |
| 100 | * we had it in bootblock_c_entry. Moving it to this point |
| 101 | * (or adding delays) fixes the issue. It seems like the processor |
| 102 | * just pauses but we don't know why. |
| 103 | */ |
| 104 | sb_reset_i2c_slaves(); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 105 | bootblock_fch_early_init(); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 106 | post_code(0x90); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 107 | } |
| 108 | |
| 109 | void bootblock_soc_init(void) |
| 110 | { |
Marshall Dawson | a5f225f | 2017-08-18 10:07:07 -0600 | [diff] [blame] | 111 | if (IS_ENABLED(CONFIG_STONEYRIDGE_UART)) |
| 112 | assert(CONFIG_UART_FOR_CONSOLE >= 0 |
| 113 | && CONFIG_UART_FOR_CONSOLE <= 1); |
| 114 | |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 115 | u32 val = cpuid_eax(1); |
| 116 | printk(BIOS_DEBUG, "Family_Model: %08x\n", val); |
| 117 | |
Raul E Rangel | d820f4b8 | 2018-08-13 10:39:03 -0600 | [diff] [blame] | 118 | bootblock_fch_init(); |
| 119 | |
Aaron Durbin | de3e84c | 2018-01-29 17:44:58 -0700 | [diff] [blame] | 120 | /* Initialize any early i2c buses. */ |
| 121 | i2c_soc_early_init(); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 122 | } |