Lijian Zhao | c319bab | 2017-07-08 18:16:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | #include <arch/byteorder.h> |
Lijian Zhao | c319bab | 2017-07-08 18:16:13 -0700 | [diff] [blame] | 16 | #include <console/console.h> |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include "spd.h" |
| 20 | |
| 21 | void mainboard_fill_dq_map_ch0(void *dq_map_ptr) |
| 22 | { |
| 23 | /* DQ byte map Ch0 */ |
| 24 | const u8 dq_map[12] = { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 25 | 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, |
Lijian Zhao | c319bab | 2017-07-08 18:16:13 -0700 | [diff] [blame] | 26 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; |
| 27 | |
| 28 | memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); |
| 29 | } |
| 30 | |
| 31 | void mainboard_fill_dq_map_ch1(void *dq_map_ptr) |
| 32 | { |
Lijian Zhao | 14cb828 | 2017-10-12 16:55:54 -0700 | [diff] [blame] | 33 | const u8 dq_map[12] = { |
Lijian Zhao | c319bab | 2017-07-08 18:16:13 -0700 | [diff] [blame] | 34 | 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, |
| 35 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; |
| 36 | |
Lijian Zhao | 14cb828 | 2017-10-12 16:55:54 -0700 | [diff] [blame] | 37 | memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); |
Lijian Zhao | c319bab | 2017-07-08 18:16:13 -0700 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) |
| 41 | { |
| 42 | /* DQS CPU<>DRAM map Ch0 */ |
Lijian Zhao | 14cb828 | 2017-10-12 16:55:54 -0700 | [diff] [blame] | 43 | const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 }; |
Lijian Zhao | c319bab | 2017-07-08 18:16:13 -0700 | [diff] [blame] | 44 | |
| 45 | const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; |
| 46 | |
| 47 | if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) |
| 48 | memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); |
| 49 | else |
| 50 | memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); |
| 51 | } |
| 52 | |
| 53 | void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) |
| 54 | { |
| 55 | /* DQS CPU<>DRAM map Ch1 */ |
Lijian Zhao | 14cb828 | 2017-10-12 16:55:54 -0700 | [diff] [blame] | 56 | const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 }; |
Lijian Zhao | c319bab | 2017-07-08 18:16:13 -0700 | [diff] [blame] | 57 | |
| 58 | const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; |
| 59 | |
| 60 | if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) |
| 61 | memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); |
| 62 | else |
| 63 | memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); |
| 64 | } |
| 65 | |
| 66 | void mainboard_fill_rcomp_res_data(void *rcomp_ptr) |
| 67 | { |
| 68 | /* Rcomp resistor */ |
| 69 | const u16 RcompResistor[3] = { 100, 100, 100 }; |
| 70 | memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); |
| 71 | } |
| 72 | |
| 73 | void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) |
| 74 | { |
| 75 | /* Rcomp target */ |
Lijian Zhao | 14cb828 | 2017-10-12 16:55:54 -0700 | [diff] [blame] | 76 | static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { |
Lijian Zhao | c319bab | 2017-07-08 18:16:13 -0700 | [diff] [blame] | 77 | 80, 40, 40, 40, 30 }; |
| 78 | |
Lijian Zhao | 14cb828 | 2017-10-12 16:55:54 -0700 | [diff] [blame] | 79 | memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); |
Lijian Zhao | c319bab | 2017-07-08 18:16:13 -0700 | [diff] [blame] | 80 | } |