| commit | c319bab3cd416d85330774f9974b41fcb49075a7 | [log] [tgz] |
|---|---|---|
| author | Lijian Zhao <lijian.zhao@intel.com> | Sat Jul 08 18:16:13 2017 -0700 |
| committer | Aaron Durbin <adurbin@chromium.org> | Wed Jul 26 21:37:14 2017 +0000 |
| tree | 7533dac79d57499e552393695b5c751a2986eb5c | |
| parent | 735779cc9aa9d6b02fadbdfc0a50fb087cce7731 [diff] |
intel/cannonlake_rvp: Split RVP boards and SPD Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support. Implement SPD entry to FSPM for both platforms, seperated platform specific DQ/DQS/Rcomp input to FSPM as well. Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>