Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Marshall Dawson | 3f6c400 | 2017-09-25 10:11:50 -0600 | [diff] [blame] | 16 | #include <chip.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 17 | #include <amdblocks/agesawrapper.h> |
chris wang | 76118a7 | 2018-10-18 18:52:58 +0800 | [diff] [blame] | 18 | #include <boardid.h> |
Chris Wang | 50c1160 | 2018-11-05 12:09:24 +0800 | [diff] [blame] | 19 | #include <gpio.h> |
| 20 | #include <console/console.h> |
| 21 | #include <soc/pci_devs.h> |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 22 | |
Marshall Dawson | 3f6c400 | 2017-09-25 10:11:50 -0600 | [diff] [blame] | 23 | #define DIMMS_PER_CHANNEL 1 |
| 24 | #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH |
| 25 | #error "Too many DIMM sockets defined for the mainboard" |
| 26 | #endif |
| 27 | |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 28 | static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { |
| 29 | DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), |
Marshall Dawson | 3f6c400 | 2017-09-25 10:11:50 -0600 | [diff] [blame] | 30 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), |
| 31 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 32 | MOTHER_BOARD_LAYERS(LAYERS_6), |
| 33 | MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 34 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 35 | CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 36 | ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 37 | CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 38 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 39 | PSO_END |
| 40 | }; |
Martin Roth | 3f68911 | 2018-12-17 13:33:10 -0700 | [diff] [blame] | 41 | /* Liara-specific 2T memory configuration */ |
chris wang | 76118a7 | 2018-10-18 18:52:58 +0800 | [diff] [blame] | 42 | static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = { |
| 43 | DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), |
| 44 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), |
| 45 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), |
| 46 | MOTHER_BOARD_LAYERS(LAYERS_6), |
| 47 | MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 48 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 49 | CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 50 | ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 51 | CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 52 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 53 | TBLDRV_CONFIG_TO_OVERRIDE(DIMMS_PER_CHANNEL, ANY_SPEED, VOLT_ANY_, |
| 54 | ANY_), |
| 55 | TBLDRV_CONFIG_ENTRY_SLOWACCMODE(1), |
| 56 | PSO_END |
| 57 | }; |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 58 | |
| 59 | void OemPostParams(AMD_POST_PARAMS *PostParams) |
| 60 | { |
Martin Roth | 3f68911 | 2018-12-17 13:33:10 -0700 | [diff] [blame] | 61 | if (IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) |
chris wang | 76118a7 | 2018-10-18 18:52:58 +0800 | [diff] [blame] | 62 | PostParams->MemConfig.PlatformMemoryConfiguration = |
| 63 | (PSO_ENTRY *)DDR4LiaraMemoryConfiguration; |
| 64 | else |
| 65 | PostParams->MemConfig.PlatformMemoryConfiguration = |
| 66 | (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; |
Richard Spiegel | 9b3da9f | 2018-02-16 14:33:59 -0700 | [diff] [blame] | 67 | /* |
| 68 | * Bank interleaving is enabled by default in AGESA. However, from AMD's |
| 69 | * explanation, bank interleaving is really chip select interleave, |
| 70 | * requiring 2 chip select arriving to the DIMM (rank interleaving). As |
| 71 | * both kahlee and grunt are hardware limited to a single chip select |
| 72 | * arriving at the DIMM, interleave will not work. This causes AGESA to |
| 73 | * throw a warning. To avoid the warning, interleaving needs to be |
| 74 | * disabled. |
| 75 | */ |
| 76 | PostParams->MemConfig.EnableBankIntlv = FALSE; |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 77 | } |
Richard Spiegel | 5d3707b | 2018-07-27 12:44:22 -0700 | [diff] [blame] | 78 | |
| 79 | void set_board_env_params(GNB_ENV_CONFIGURATION *params) |
| 80 | { |
Chris Wang | 50c1160 | 2018-11-05 12:09:24 +0800 | [diff] [blame] | 81 | const struct soc_amd_stoneyridge_config *cfg; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 82 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
Chris Wang | 50c1160 | 2018-11-05 12:09:24 +0800 | [diff] [blame] | 83 | if (!dev || !dev->chip_info) { |
| 84 | printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree config\n"); |
| 85 | return; |
| 86 | } |
| 87 | cfg = dev->chip_info; |
| 88 | if (cfg->lvds_poseq_blon_to_varybl && cfg->lvds_poseq_varybl_to_blon) { |
| 89 | /* |
| 90 | * GPIO 133 - Backlight enable (active low) |
| 91 | * Pass control of the backlight to the video BIOS |
| 92 | */ |
| 93 | gpio_set(GPIO_133, 0); |
| 94 | printk(BIOS_INFO, "Change panel init timing\n"); |
| 95 | params->LvdsPowerOnSeqVaryBlToBlon = |
| 96 | cfg->lvds_poseq_varybl_to_blon; |
| 97 | params->LvdsPowerOnSeqBlonToVaryBl = |
| 98 | cfg->lvds_poseq_blon_to_varybl; |
| 99 | printk(BIOS_INFO, "LvdsPowerOnSeqVaryBlToBlon: %dms\n", |
| 100 | (params->LvdsPowerOnSeqVaryBlToBlon)*4); |
| 101 | printk(BIOS_INFO, "LvdsPowerOnSeqBlonToVaryBl: %dms\n", |
| 102 | (params->LvdsPowerOnSeqBlonToVaryBl)*4); |
| 103 | } |
Richard Spiegel | 5d3707b | 2018-07-27 12:44:22 -0700 | [diff] [blame] | 104 | params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE; |
| 105 | } |