Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
| 4 | #include <string.h> |
| 5 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 7 | #include <device/pci_def.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 8 | |
| 9 | #include "gm45.h" |
| 10 | |
| 11 | void init_iommu() |
| 12 | { |
| 13 | /* FIXME: proper test? */ |
| 14 | int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; |
| 15 | int stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); |
| 16 | |
| 17 | MCHBAR32(0x28) = IOMMU_BASE1 | 1; /* HDA @ 0:1b.0 */ |
| 18 | if (stepping != STEPPING_B2) { |
| 19 | /* The official workaround is to run SMM every 64ms. |
| 20 | The only winning move is not to play. */ |
| 21 | MCHBAR32(0x18) = IOMMU_BASE2 | 1; /* IGD @ 0:2.0-1 */ |
| 22 | } else { |
| 23 | /* write-once, so lock it down */ |
| 24 | MCHBAR32(0x18) = 0; /* disable IOMMU for IGD @ 0:2.0-1 */ |
| 25 | } |
| 26 | if (me_active) { |
| 27 | MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */ |
Damien Zammit | 88af372 | 2016-08-27 00:35:48 +1000 | [diff] [blame] | 28 | } else { |
| 29 | MCHBAR32(0x10) = 0; /* disable IOMMU for ME */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 30 | } |
| 31 | MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ |
| 32 | |
| 33 | /* clear GTT */ |
Elyes HAOUAS | ef20ecc | 2018-10-04 13:50:14 +0200 | [diff] [blame] | 34 | u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 35 | if (gtt & 0x400) { /* VT mode */ |
Elyes HAOUAS | d13bd05 | 2020-04-22 16:39:20 +0200 | [diff] [blame] | 36 | const pci_devfn_t igd = PCI_DEV(0, 2, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 37 | |
| 38 | /* setup somewhere */ |
| 39 | u8 cmd = pci_read_config8(igd, PCI_COMMAND); |
| 40 | cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 41 | pci_write_config8(igd, PCI_COMMAND, cmd); |
Elyes HAOUAS | fd051dc | 2018-07-08 12:39:34 +0200 | [diff] [blame] | 42 | void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 43 | |
| 44 | /* clear GTT, 2MB is enough (and should be safe) */ |
| 45 | memset(bar, 0, 2<<20); |
| 46 | |
| 47 | /* and now disable again */ |
| 48 | cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 49 | pci_write_config8(igd, PCI_COMMAND, cmd); |
| 50 | pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); |
| 51 | } |
| 52 | |
| 53 | if (stepping == STEPPING_B3) { |
| 54 | MCHBAR8(0xffc) |= 1 << 4; |
Elyes HAOUAS | d13bd05 | 2020-04-22 16:39:20 +0200 | [diff] [blame] | 55 | const pci_devfn_t peg = PCI_DEV(0, 1, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 56 | /* FIXME: proper test? */ |
| 57 | if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) { |
| 58 | int val = pci_read_config32(peg, 0xfc) | (1 << 15); |
| 59 | pci_write_config32(peg, 0xfc, val); |
| 60 | } |
| 61 | } |
| 62 | |
| 63 | /* final */ |
| 64 | MCHBAR8(0x94) |= 1 << 3; |
| 65 | } |