commit fd051dc018346e5947d9d8733e269fc5020236ba
author Elyes HAOUAS <ehaouas@noos.fr> Sun Jul 08 12:39:34 2018 +0200
committer Patrick Georgi <pgeorgi@google.com> Mon Jul 09 09:29:53 2018 +0000
tree d12a70629b7565c20643c97ca8a933c4344e5b7b
parent 95bca33efa280e606f7c6d41541cec67c0eb227f

src/northbridge: Use "foo *bar" instead of "foo* bar"

Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

src/northbridge/intel/gm45/iommu.c

diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 77aba94..0108116 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -54,7 +54,7 @@
 		u8 cmd = pci_read_config8(igd, PCI_COMMAND);
 		cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 		pci_write_config8(igd, PCI_COMMAND, cmd);
-		void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
+		void *bar = (void *)pci_read_config32(igd, PCI_BASE_ADDRESS_0);
 
 		/* clear GTT, 2MB is enough (and should be safe) */
 		memset(bar, 0, 2<<20);