Angel Pons | 96d93d1 | 2020-04-05 13:22:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 5 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 6 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 7 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 8 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 9 | #include <southbridge/intel/common/gpio.h> |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 10 | #include "ec/compal/ene932/ec.h" |
| 11 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 12 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 13 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 14 | /* |
| 15 | * GFX INTA -> PIRQA (MSI) |
| 16 | * D28IP_P2IP WLAN INTA -> PIRQB |
| 17 | * D28IP_P3IP ETH0 INTC -> PIRQD |
| 18 | * D29IP_E1P EHCI1 INTA -> PIRQE |
| 19 | * D26IP_E2P EHCI2 INTA -> PIRQE |
| 20 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 21 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 22 | * D31IP_TTIP THRT INTC -> PIRQH |
| 23 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 24 | * |
| 25 | * Trackpad DVT PIRQA (16) |
| 26 | * Trackpad DVT PIRQE (20) |
| 27 | */ |
| 28 | |
| 29 | /* Device interrupt pin register (board specific) */ |
| 30 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 31 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 32 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 33 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 34 | RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | |
| 35 | (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) | |
| 36 | (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) | |
| 37 | (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); |
| 38 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 39 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 40 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 41 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 42 | |
| 43 | /* Device interrupt route registers */ |
| 44 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 45 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 46 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 47 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 48 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 49 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 50 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 51 | } |
| 52 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 53 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
| 54 | { |
| 55 | struct pei_data pei_data_template = { |
Edward O'Callaghan | f5037bd | 2014-05-23 08:36:01 +1000 | [diff] [blame] | 56 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 57 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 58 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | f5037bd | 2014-05-23 08:36:01 +1000 | [diff] [blame] | 59 | .epbar = DEFAULT_EPBAR, |
| 60 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame^] | 61 | .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, |
Edward O'Callaghan | f5037bd | 2014-05-23 08:36:01 +1000 | [diff] [blame] | 62 | .wdbbar = 0x4000000, |
| 63 | .wdbsize = 0x1000, |
| 64 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 65 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | f5037bd | 2014-05-23 08:36:01 +1000 | [diff] [blame] | 66 | .pmbase = DEFAULT_PMBASE, |
| 67 | .gpiobase = DEFAULT_GPIOBASE, |
| 68 | .thermalbase = 0xfed08000, |
| 69 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 70 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 71 | .spd_addresses = { 0xA0, 0x00,0xA4,0x00 }, |
| 72 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 73 | .ec_present = 1, |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 74 | // 0 = leave channel enabled |
| 75 | // 1 = disable dimm 0 on channel |
| 76 | // 2 = disable dimm 1 on channel |
| 77 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | f5037bd | 2014-05-23 08:36:01 +1000 | [diff] [blame] | 78 | .dimm_channel0_disabled = 2, |
| 79 | .dimm_channel1_disabled = 2, |
| 80 | .max_ddr3_freq = 1600, |
| 81 | .usb_port_config = { |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 82 | /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ |
| 83 | { 0, 3, 0x0000 }, /* P0: Empty */ |
| 84 | { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ |
| 85 | { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ |
| 86 | { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */ |
| 87 | { 0, 3, 0x0000 }, /* P4: Empty */ |
| 88 | { 0, 3, 0x0000 }, /* P5: Empty */ |
| 89 | { 0, 3, 0x0000 }, /* P6: Empty */ |
| 90 | { 0, 3, 0x0000 }, /* P7: Empty */ |
| 91 | /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ |
| 92 | { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */ |
| 93 | { 0, 4, 0x0000 }, /* P9: Empty */ |
| 94 | { 1, 4, 0x0040 }, /* P10: Camera (no OC) */ |
| 95 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 96 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 97 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 98 | }, |
| 99 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 100 | *pei_data = pei_data_template; |
| 101 | } |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 102 | |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 103 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 104 | /* enabled power USB oc pin */ |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 105 | { 0, 0, -1 }, /* P0: Empty */ |
| 106 | { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ |
| 107 | { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ |
| 108 | { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */ |
| 109 | { 0, 0, -1 }, /* P4: Empty */ |
| 110 | { 0, 0, -1 }, /* P5: Empty */ |
| 111 | { 0, 0, -1 }, /* P6: Empty */ |
| 112 | { 0, 0, -1 }, /* P7: Empty */ |
| 113 | /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ |
| 114 | { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */ |
| 115 | { 0, 0, -1 }, /* P9: Empty */ |
| 116 | { 1, 0, -1 }, /* P10: Camera (no OC) */ |
| 117 | { 0, 0, -1 }, /* P11: Empty */ |
| 118 | { 0, 0, -1 }, /* P12: Empty */ |
| 119 | { 0, 0, -1 }, /* P13: Empty */ |
| 120 | }; |
| 121 | |
Peter Lemenkov | 498f1cc | 2019-02-07 10:48:10 +0100 | [diff] [blame] | 122 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 123 | { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 124 | read_spd(&spd[0], 0x50, id_only); |
| 125 | read_spd(&spd[2], 0x52, id_only); |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 126 | } |
| 127 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 128 | int mainboard_should_reset_usb(int s3resume) |
| 129 | { |
| 130 | return !s3resume; |
Stefan Reinauer | a7198b3 | 2012-12-11 16:00:47 -0800 | [diff] [blame] | 131 | } |