| Elyes HAOUAS | 36787b0 | 2020-05-07 12:07:24 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| Uwe Hermann | b7fec82 | 2009-08-25 12:25:36 +0000 | [diff] [blame] | 2 | |
| 3 | config NORTHBRIDGE_INTEL_I440BX |
| 4 | bool |
| Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 5 | select NO_ECAM_MMCONF_SUPPORT |
| Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 6 | select HAVE_DEBUG_RAM_SETUP |
| Julius Werner | baf27db | 2019-10-02 17:28:56 -0700 | [diff] [blame] | 7 | select NO_CBFS_MCACHE |
| Elyes Haouas | bfcea14 | 2022-12-11 08:55:49 +0100 | [diff] [blame] | 8 | select NO_DDR5 |
| 9 | select NO_LPDDR4 |
| 10 | select NO_DDR4 |
| 11 | select NO_DDR3 |
| 12 | select NO_DDR2 |
| Patrick Georgi | 88f55b2 | 2009-09-25 18:43:02 +0000 | [diff] [blame] | 13 | |
| Keith Hui | 9c1e1f0 | 2010-03-13 20:16:48 +0000 | [diff] [blame] | 14 | config SDRAMPWR_4DIMM |
| 15 | bool |
| 16 | depends on NORTHBRIDGE_INTEL_I440BX |
| 17 | default n |
| 18 | help |
| 19 | This option affects how the SDRAMC register is programmed. |
| 20 | Memory clock signals will not be routed properly if this option |
| 21 | is set wrong. |
| Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 22 | |
| Keith Hui | 9c1e1f0 | 2010-03-13 20:16:48 +0000 | [diff] [blame] | 23 | If your board has 4 DIMM slots, you must use select this option, in |
| 24 | your Kconfig file of the board. On boards with 3 DIMM slots, |
| 25 | do _not_ select this option. |