| Elyes HAOUAS | 36787b0 | 2020-05-07 12:07:24 +0200 | [diff] [blame^] | 1 | # This file is part of the coreboot project. |
| 2 | # SPDX-License-Identifier: GPL-2.0-only |
| Uwe Hermann | b7fec82 | 2009-08-25 12:25:36 +0000 | [diff] [blame] | 3 | |
| 4 | config NORTHBRIDGE_INTEL_I440BX |
| 5 | bool |
| Kyösti Mälkki | 3d15e10 | 2016-11-29 16:46:56 +0200 | [diff] [blame] | 6 | select NO_MMCONF_SUPPORT |
| Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 7 | select HAVE_DEBUG_RAM_SETUP |
| Arthur Heymans | 1fa240a | 2019-11-12 12:05:38 +0100 | [diff] [blame] | 8 | select NO_BOOTBLOCK_CONSOLE |
| Patrick Georgi | 88f55b2 | 2009-09-25 18:43:02 +0000 | [diff] [blame] | 9 | |
| Keith Hui | 9c1e1f0 | 2010-03-13 20:16:48 +0000 | [diff] [blame] | 10 | config SDRAMPWR_4DIMM |
| 11 | bool |
| 12 | depends on NORTHBRIDGE_INTEL_I440BX |
| 13 | default n |
| 14 | help |
| 15 | This option affects how the SDRAMC register is programmed. |
| 16 | Memory clock signals will not be routed properly if this option |
| 17 | is set wrong. |
| Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 18 | |
| Keith Hui | 9c1e1f0 | 2010-03-13 20:16:48 +0000 | [diff] [blame] | 19 | If your board has 4 DIMM slots, you must use select this option, in |
| 20 | your Kconfig file of the board. On boards with 3 DIMM slots, |
| 21 | do _not_ select this option. |