Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
Iru Cai | d7ee9dd | 2016-02-24 15:03:58 +0800 | [diff] [blame] | 3 | #ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H |
| 4 | #define NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H |
| 5 | |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 6 | #include <drivers/intel/gma/i915.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 7 | #include <stdbool.h> |
| 8 | #include <stdint.h> |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 9 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 10 | /* |
| 11 | * Digital Port Hotplug Enable: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 12 | * 0x04 = Enabled, 2ms short pulse |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 13 | * 0x05 = Enabled, 4.5ms short pulse |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 14 | * 0x06 = Enabled, 6ms short pulse |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 15 | * 0x07 = Enabled, 100ms short pulse |
| 16 | */ |
| 17 | struct northbridge_intel_sandybridge_config { |
| 18 | u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ |
| 19 | u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ |
| 20 | u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ |
| 21 | |
Angel Pons | dc0c081 | 2020-09-02 19:17:30 +0200 | [diff] [blame] | 22 | enum { |
| 23 | PANEL_PORT_LVDS = 0, |
| 24 | PANEL_PORT_DP_A = 1, /* Also known as eDP */ |
| 25 | PANEL_PORT_DP_C = 2, |
| 26 | PANEL_PORT_DP_D = 3, |
| 27 | } gpu_panel_port_select; |
| 28 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 29 | u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ |
| 30 | u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ |
| 31 | u16 gpu_panel_power_down_delay; /* T3 time sequence */ |
| 32 | u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ |
| 33 | u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 34 | |
| 35 | u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ |
| 36 | u32 gpu_pch_backlight; /* PCH Backlight PWM value */ |
Vladimir Serbinenko | 1783a3c | 2014-02-23 00:10:35 +0100 | [diff] [blame] | 37 | |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 38 | /* |
| 39 | * Maximum memory clock. |
| 40 | * For example 666 for DDR3-1333, or 800 for DDR3-1600 |
| 41 | */ |
| 42 | u16 max_mem_clock_mhz; |
| 43 | |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 44 | struct i915_gpu_controller_info gfx; |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 45 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 46 | /* Data for RAM init */ |
| 47 | |
Keith Hui | 1e9601c | 2023-07-15 12:08:51 -0400 | [diff] [blame] | 48 | /* DIMM SPD address. */ |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 49 | u8 spd_addresses[4]; |
| 50 | |
| 51 | /* PEI data for RAM init and early silicon init */ |
| 52 | u8 ts_addresses[4]; |
| 53 | |
| 54 | bool ec_present; |
| 55 | bool ddr3lv_support; |
| 56 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 57 | /* |
| 58 | * N mode functionality. Leave this setting at 0. |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 59 | * 0 Auto |
| 60 | * 1 1N |
| 61 | * 2 2N |
| 62 | */ |
| 63 | enum { |
| 64 | DDR_NMODE_AUTO = 0, |
| 65 | DDR_NMODE_1N, |
| 66 | DDR_NMODE_2N, |
| 67 | } nmode; |
| 68 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 69 | /* |
| 70 | * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows for DIMM SPD data to |
| 71 | * specify whether double-rate is required for extended operating temperature range. |
| 72 | * |
| 73 | * 0 Enable double rate based upon temperature thresholds |
| 74 | * 1 Normal rate |
| 75 | * 2 Always enable double rate |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 76 | */ |
| 77 | enum { |
| 78 | DDR_REFRESH_RATE_TEMP_THRES = 0, |
| 79 | DDR_REFRESH_REATE_NORMAL, |
| 80 | DDR_REFRESH_RATE_DOUBLE, |
| 81 | } ddr_refresh_rate_config; |
| 82 | |
| 83 | /* |
| 84 | * USB Port Configuration: |
| 85 | * [0] = enable |
| 86 | * [1] = overcurrent pin |
| 87 | * [2] = length |
| 88 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 89 | * Ports 0-7 can be mapped to OC0-OC3 |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 90 | * Ports 8-13 can be mapped to OC4-OC7 |
| 91 | * |
| 92 | * Port Length |
| 93 | * MOBILE: |
| 94 | * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) |
| 95 | * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) |
| 96 | * DESKTOP: |
| 97 | * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) |
| 98 | * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) |
| 99 | * < 0x150 = Setting 3 (back panel, 13-15in, highest tx amplitude) |
| 100 | */ |
| 101 | u16 usb_port_config[16][3]; |
| 102 | |
| 103 | struct { |
| 104 | /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ |
| 105 | u8 mode : 2; |
| 106 | /* 4 bit mask, 1: switchable, 0: not switchable */ |
| 107 | u8 hs_port_switch_mask : 4; |
| 108 | /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ |
| 109 | u8 preboot_support : 1; |
| 110 | /* 0: Disable, 1: Enable */ |
| 111 | u8 xhci_streams : 1; |
| 112 | } usb3; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 113 | }; |
Iru Cai | d7ee9dd | 2016-02-24 15:03:58 +0800 | [diff] [blame] | 114 | |
| 115 | #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ |