Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
Iru Cai | d7ee9dd | 2016-02-24 15:03:58 +0800 | [diff] [blame] | 16 | #ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H |
| 17 | #define NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H |
| 18 | |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 19 | #include <drivers/intel/gma/i915.h> |
| 20 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 21 | /* |
| 22 | * Digital Port Hotplug Enable: |
| 23 | * 0x04 = Enabled, 2ms short pulse |
| 24 | * 0x05 = Enabled, 4.5ms short pulse |
| 25 | * 0x06 = Enabled, 6ms short pulse |
| 26 | * 0x07 = Enabled, 100ms short pulse |
| 27 | */ |
| 28 | struct northbridge_intel_sandybridge_config { |
| 29 | u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ |
| 30 | u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ |
| 31 | u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ |
| 32 | |
| 33 | u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ |
| 34 | u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ |
| 35 | u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ |
| 36 | u16 gpu_panel_power_down_delay; /* T3 time sequence */ |
| 37 | u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ |
| 38 | u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 39 | |
| 40 | u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ |
| 41 | u32 gpu_pch_backlight; /* PCH Backlight PWM value */ |
Vladimir Serbinenko | 1783a3c | 2014-02-23 00:10:35 +0100 | [diff] [blame] | 42 | |
Alexandru Gagniuc | 8b2c8f1 | 2015-02-17 04:31:01 -0600 | [diff] [blame] | 43 | /* |
| 44 | * Maximum memory clock. |
| 45 | * For example 666 for DDR3-1333, or 800 for DDR3-1600 |
| 46 | */ |
| 47 | u16 max_mem_clock_mhz; |
| 48 | |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 49 | struct i915_gpu_controller_info gfx; |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame^] | 50 | |
| 51 | /* |
| 52 | * Maximum PCI mmio size in MiB. |
| 53 | */ |
| 54 | u16 pci_mmio_size; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 55 | }; |
Iru Cai | d7ee9dd | 2016-02-24 15:03:58 +0800 | [diff] [blame] | 56 | |
| 57 | #endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ |