Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stddef.h> |
| 17 | #include <arch/cpu.h> |
| 18 | #include <arch/io.h> |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 19 | #include <arch/early_variables.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 20 | #include <console/console.h> |
Aaron Durbin | bd74a4b | 2015-03-06 23:17:33 -0600 | [diff] [blame] | 21 | #include <cbfs.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 22 | #include <cbmem.h> |
| 23 | #include <cpu/x86/mtrr.h> |
Aaron Durbin | 3e0eea1 | 2013-10-28 11:20:35 -0500 | [diff] [blame] | 24 | #if CONFIG_EC_GOOGLE_CHROMEEC |
| 25 | #include <ec/google/chromeec/ec.h> |
| 26 | #endif |
Aaron Durbin | a8e9b63 | 2013-10-30 15:46:07 -0500 | [diff] [blame] | 27 | #include <elog.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 28 | #include <program_loading.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 29 | #include <romstage_handoff.h> |
Aaron Durbin | bd74a4b | 2015-03-06 23:17:33 -0600 | [diff] [blame] | 30 | #include <stage_cache.h> |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 31 | #include <timestamp.h> |
Vladimir Serbinenko | 0e90dae | 2015-05-18 10:29:06 +0200 | [diff] [blame] | 32 | #include <tpm.h> |
Aaron Durbin | ebf7ec5 | 2013-11-14 13:47:08 -0600 | [diff] [blame] | 33 | #include <vendorcode/google/chromeos/chromeos.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 34 | #include <soc/gpio.h> |
| 35 | #include <soc/iomap.h> |
| 36 | #include <soc/lpc.h> |
| 37 | #include <soc/pci_devs.h> |
| 38 | #include <soc/pmc.h> |
| 39 | #include <soc/reset.h> |
| 40 | #include <soc/romstage.h> |
| 41 | #include <soc/smm.h> |
| 42 | #include <soc/spi.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 43 | |
| 44 | /* The cache-as-ram assembly file calls romstage_main() after setting up |
| 45 | * cache-as-ram. romstage_main() will then call the mainboards's |
| 46 | * mainboard_romstage_entry() function. That function then calls |
| 47 | * romstage_common() below. The reason for the back and forth is to provide |
| 48 | * common entry point from cache-as-ram while still allowing for code sharing. |
| 49 | * Because we can't use global variables the stack is used for allocations -- |
| 50 | * thus the need to call back and forth. */ |
| 51 | |
| 52 | static void *setup_stack_and_mttrs(void); |
| 53 | |
| 54 | static void program_base_addresses(void) |
| 55 | { |
| 56 | uint32_t reg; |
| 57 | const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
| 58 | |
| 59 | /* Memory Mapped IO registers. */ |
| 60 | reg = PMC_BASE_ADDRESS | 2; |
| 61 | pci_write_config32(lpc_dev, PBASE, reg); |
| 62 | reg = IO_BASE_ADDRESS | 2; |
| 63 | pci_write_config32(lpc_dev, IOBASE, reg); |
| 64 | reg = ILB_BASE_ADDRESS | 2; |
| 65 | pci_write_config32(lpc_dev, IBASE, reg); |
| 66 | reg = SPI_BASE_ADDRESS | 2; |
| 67 | pci_write_config32(lpc_dev, SBASE, reg); |
| 68 | reg = MPHY_BASE_ADDRESS | 2; |
| 69 | pci_write_config32(lpc_dev, MPBASE, reg); |
Aaron Durbin | a64ef62 | 2013-10-03 12:56:37 -0500 | [diff] [blame] | 70 | reg = PUNIT_BASE_ADDRESS | 2; |
| 71 | pci_write_config32(lpc_dev, PUBASE, reg); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 72 | reg = RCBA_BASE_ADDRESS | 1; |
| 73 | pci_write_config32(lpc_dev, RCBA, reg); |
| 74 | |
| 75 | /* IO Port Registers. */ |
| 76 | reg = ACPI_BASE_ADDRESS | 2; |
| 77 | pci_write_config32(lpc_dev, ABASE, reg); |
| 78 | reg = GPIO_BASE_ADDRESS | 2; |
| 79 | pci_write_config32(lpc_dev, GBASE, reg); |
| 80 | } |
| 81 | |
Aaron Durbin | 6f9947a | 2013-11-18 11:16:20 -0600 | [diff] [blame] | 82 | static void spi_init(void) |
| 83 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 84 | u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); |
| 85 | u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 86 | uint32_t reg; |
| 87 | |
| 88 | /* Disable generating SMI when setting WPD bit. */ |
| 89 | write32(scs, read32(scs) & ~SMIWPEN); |
| 90 | /* |
| 91 | * Enable caching and prefetching in the SPI controller. Disable |
| 92 | * the SMM-only BIOS write and set WPD bit. |
| 93 | */ |
| 94 | reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; |
| 95 | reg &= ~EISS; |
| 96 | write32(bcr, reg); |
Aaron Durbin | 6f9947a | 2013-11-18 11:16:20 -0600 | [diff] [blame] | 97 | } |
| 98 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 99 | /* Entry from cache-as-ram.inc. */ |
| 100 | void * asmlinkage romstage_main(unsigned long bist, |
| 101 | uint32_t tsc_low, uint32_t tsc_hi) |
| 102 | { |
| 103 | struct romstage_params rp = { |
| 104 | .bist = bist, |
| 105 | .mrc_params = NULL, |
| 106 | }; |
| 107 | |
| 108 | /* Save initial timestamp from bootblock. */ |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 109 | timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); |
| 110 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 111 | /* Save romstage begin */ |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 112 | timestamp_add_now(TS_START_ROMSTAGE); |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 113 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 114 | program_base_addresses(); |
| 115 | |
Aaron Durbin | fd039f7 | 2013-10-04 11:11:52 -0500 | [diff] [blame] | 116 | tco_disable(); |
| 117 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 118 | byt_config_com1_and_enable(); |
| 119 | |
| 120 | console_init(); |
| 121 | |
Aaron Durbin | 6f9947a | 2013-11-18 11:16:20 -0600 | [diff] [blame] | 122 | spi_init(); |
| 123 | |
Aaron Durbin | bb3ee83 | 2013-10-07 17:12:20 -0500 | [diff] [blame] | 124 | set_max_freq(); |
| 125 | |
Aaron Durbin | 189aa3e | 2013-10-04 11:17:45 -0500 | [diff] [blame] | 126 | punit_init(); |
| 127 | |
Aaron Durbin | ecf9086 | 2013-09-24 12:36:14 -0500 | [diff] [blame] | 128 | gfx_init(); |
| 129 | |
Aaron Durbin | 3e0eea1 | 2013-10-28 11:20:35 -0500 | [diff] [blame] | 130 | #if CONFIG_EC_GOOGLE_CHROMEEC |
| 131 | /* Ensure the EC is in the right mode for recovery */ |
| 132 | google_chromeec_early_init(); |
| 133 | #endif |
| 134 | |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 135 | /* Call into mainboard. */ |
| 136 | mainboard_romstage_entry(&rp); |
| 137 | |
| 138 | return setup_stack_and_mttrs(); |
| 139 | } |
| 140 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 141 | static struct chipset_power_state power_state CAR_GLOBAL; |
| 142 | |
Aaron Durbin | 41607a4 | 2015-06-09 13:54:10 -0500 | [diff] [blame] | 143 | static void migrate_power_state(int is_recovery) |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 144 | { |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 145 | struct chipset_power_state *ps_cbmem; |
| 146 | struct chipset_power_state *ps_car; |
| 147 | |
| 148 | ps_car = car_get_var_ptr(&power_state); |
| 149 | ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); |
| 150 | |
| 151 | if (ps_cbmem == NULL) { |
| 152 | printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); |
| 153 | return; |
| 154 | } |
| 155 | memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); |
| 156 | } |
Kyösti Mälkki | 4fbac46 | 2015-01-07 04:48:43 +0200 | [diff] [blame] | 157 | ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 158 | |
| 159 | static struct chipset_power_state *fill_power_state(void) |
| 160 | { |
| 161 | struct chipset_power_state *ps = car_get_var_ptr(&power_state); |
| 162 | |
| 163 | ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 164 | ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); |
| 165 | ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 166 | ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); |
| 167 | ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); |
| 168 | ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 169 | ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); |
| 170 | ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); |
| 171 | ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 172 | |
| 173 | printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", |
| 174 | ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); |
| 175 | printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", |
| 176 | ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); |
| 177 | printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", |
| 178 | ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); |
| 179 | |
| 180 | return ps; |
| 181 | } |
| 182 | |
| 183 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 184 | static int chipset_prev_sleep_state(struct chipset_power_state *ps) |
| 185 | { |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 186 | /* Default to S0. */ |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 187 | int prev_sleep_state = ACPI_S0; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 188 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 189 | if (ps->pm1_sts & WAK_STS) { |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 190 | switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { |
| 191 | case ACPI_S3: |
| 192 | if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) |
| 193 | prev_sleep_state = ACPI_S3; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 194 | break; |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 195 | case ACPI_S5: |
| 196 | prev_sleep_state = ACPI_S5; |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 197 | break; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 198 | } |
| 199 | /* Clear SLP_TYP. */ |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 200 | outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 201 | } |
| 202 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 203 | if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 204 | prev_sleep_state = ACPI_S5; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 205 | } |
| 206 | |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 207 | return prev_sleep_state; |
| 208 | } |
| 209 | |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 210 | /* Entry from the mainboard. */ |
| 211 | void romstage_common(struct romstage_params *params) |
| 212 | { |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 213 | struct chipset_power_state *ps; |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 214 | int prev_sleep_state; |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 215 | |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 216 | timestamp_add_now(TS_BEFORE_INITRAM); |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 217 | |
Aaron Durbin | 00bf3db | 2014-01-09 10:33:23 -0600 | [diff] [blame] | 218 | ps = fill_power_state(); |
| 219 | prev_sleep_state = chipset_prev_sleep_state(ps); |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 220 | |
| 221 | printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); |
| 222 | |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 223 | #if CONFIG_ELOG_BOOT_COUNT |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 224 | if (prev_sleep_state != ACPI_S3) |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 225 | boot_count_increment(); |
| 226 | #endif |
| 227 | |
| 228 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 229 | /* Initialize RAM */ |
Aaron Durbin | 6e32893 | 2013-11-06 12:04:50 -0600 | [diff] [blame] | 230 | raminit(params->mrc_params, prev_sleep_state); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 231 | |
Kyösti Mälkki | 4175927 | 2014-12-31 21:11:51 +0200 | [diff] [blame] | 232 | timestamp_add_now(TS_AFTER_INITRAM); |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 233 | |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 234 | romstage_handoff_init(prev_sleep_state == ACPI_S3); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 235 | |
Denis 'GNUtoo' Carikli | 0e92bb0 | 2016-02-20 17:32:03 +0100 | [diff] [blame] | 236 | if (IS_ENABLED(CONFIG_LPC_TPM)) { |
Aaron Durbin | f5cfaa3 | 2016-07-13 23:20:07 -0500 | [diff] [blame] | 237 | init_tpm(prev_sleep_state == ACPI_S3); |
Vladimir Serbinenko | 0e90dae | 2015-05-18 10:29:06 +0200 | [diff] [blame] | 238 | } |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 239 | } |
| 240 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 241 | void asmlinkage romstage_after_car(void) |
| 242 | { |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 243 | /* Load the ramstage. */ |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 244 | run_ramstage(); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 245 | while (1); |
| 246 | } |
| 247 | |
| 248 | static inline uint32_t *stack_push(u32 *stack, u32 value) |
| 249 | { |
| 250 | stack = &stack[-1]; |
| 251 | *stack = value; |
| 252 | return stack; |
| 253 | } |
| 254 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 255 | /* setup_stack_and_mttrs() determines the stack to use after |
| 256 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
| 257 | static void *setup_stack_and_mttrs(void) |
| 258 | { |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 259 | int num_mtrrs; |
| 260 | uint32_t *slot; |
| 261 | uint32_t mtrr_mask_upper; |
| 262 | uint32_t top_of_ram; |
| 263 | |
| 264 | /* Top of stack needs to be aligned to a 4-byte boundary. */ |
Kyösti Mälkki | de01136 | 2016-11-17 22:39:29 +0200 | [diff] [blame] | 265 | slot = (void *)romstage_ram_stack_top(); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 266 | num_mtrrs = 0; |
| 267 | |
| 268 | /* The upper bits of the MTRR mask need to set according to the number |
| 269 | * of physical address bits. */ |
| 270 | mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; |
| 271 | |
| 272 | /* The order for each MTRR is value then base with upper 32-bits of |
| 273 | * each value coming before the lower 32-bits. The reasoning for |
| 274 | * this ordering is to create a stack layout like the following: |
| 275 | * +0: Number of MTRRs |
| 276 | * +4: MTRR base 0 31:0 |
| 277 | * +8: MTRR base 0 63:32 |
| 278 | * +12: MTRR mask 0 31:0 |
| 279 | * +16: MTRR mask 0 63:32 |
| 280 | * +20: MTRR base 1 31:0 |
| 281 | * +24: MTRR base 1 63:32 |
| 282 | * +28: MTRR mask 1 31:0 |
| 283 | * +32: MTRR mask 1 63:32 |
| 284 | */ |
| 285 | |
| 286 | /* Cache the ROM as WP just below 4GiB. */ |
| 287 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 288 | slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 289 | slot = stack_push(slot, 0); /* upper base */ |
| 290 | slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); |
| 291 | num_mtrrs++; |
| 292 | |
Kyösti Mälkki | 65cc526 | 2016-06-19 20:38:41 +0300 | [diff] [blame] | 293 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 294 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
Kyösti Mälkki | 65cc526 | 2016-06-19 20:38:41 +0300 | [diff] [blame] | 295 | slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 296 | slot = stack_push(slot, 0); /* upper base */ |
| 297 | slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); |
| 298 | num_mtrrs++; |
| 299 | |
| 300 | top_of_ram = (uint32_t)cbmem_top(); |
Elyes HAOUAS | 038e724 | 2016-07-29 18:31:16 +0200 | [diff] [blame] | 301 | /* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 302 | * start of the TSEG region. It is required to be 8MiB aligned. Set |
| 303 | * this area as cacheable so it can be used later for ramstage before |
| 304 | * setting up the entire RAM as cacheable. */ |
| 305 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 306 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 307 | slot = stack_push(slot, 0); /* upper base */ |
| 308 | slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); |
| 309 | num_mtrrs++; |
| 310 | |
Elyes HAOUAS | 038e724 | 2016-07-29 18:31:16 +0200 | [diff] [blame] | 311 | /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 312 | * region resides. However, it is not restricted to SMM mode until |
| 313 | * SMM has been relocated. By setting the region to cacheable it |
| 314 | * provides faster access when relocating the SMM handler as well |
| 315 | * as using the TSEG region for other purposes. */ |
| 316 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 317 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 318 | slot = stack_push(slot, 0); /* upper base */ |
| 319 | slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); |
| 320 | num_mtrrs++; |
| 321 | |
| 322 | /* Save the number of MTRRs to setup. Return the stack location |
| 323 | * pointing to the number of MTRRs. */ |
| 324 | slot = stack_push(slot, num_mtrrs); |
| 325 | |
| 326 | return slot; |
| 327 | } |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 328 | |
Paul Kocialkowski | a400327 | 2015-09-03 11:27:27 +0200 | [diff] [blame] | 329 | int get_sw_write_protect_state(void) |
Shawn Nematbakhsh | 565d409 | 2014-03-14 14:06:45 -0700 | [diff] [blame] | 330 | { |
| 331 | u8 status; |
| 332 | /* Return unprotected status if status read fails. */ |
| 333 | return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80)); |
| 334 | } |