intel post-car: Increase stacktop alignment
Align top of stack to 8 bytes, value documented as FSP1.1 requirement.
Also fix some cases of uintptr_t casted to unsigned long.
Change-Id: I5bbd100eeb673417da205a2c2c3410fef1af61f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17461
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 9cf110e..a61b571 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -261,15 +261,13 @@
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void *setup_stack_and_mttrs(void)
{
- unsigned long top_of_stack;
int num_mtrrs;
uint32_t *slot;
uint32_t mtrr_mask_upper;
uint32_t top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */
- top_of_stack = romstage_ram_stack_top() & ~3;
- slot = (void *)top_of_stack;
+ slot = (void *)romstage_ram_stack_top();
num_mtrrs = 0;
/* The upper bits of the MTRR mask need to set according to the number