| Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 3 | |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
| 7 | #include <device/pci_def.h> |
| 8 | #include <amdblocks/sata.h> |
| 9 | #include <soc/southbridge.h> |
| 10 | |
| 11 | void soc_enable_sata_features(struct device *dev) |
| 12 | { |
| 13 | u8 *ahci_ptr; |
| 14 | u32 misc_ctl, cap_cfg; |
| 15 | |
| 16 | u32 temp; |
| 17 | |
| 18 | /* unlock the write-protect */ |
| 19 | misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG); |
| 20 | misc_ctl |= SATA_MISC_SUBCLASS_WREN; |
| 21 | pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl); |
| 22 | |
| 23 | /* set the SATA AHCI mode to allow port expanders */ |
| 24 | ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN( |
| 25 | pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256); |
| 26 | |
| 27 | cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG); |
| 28 | cap_cfg |= SATA_CAPABILITY_SPM; |
| 29 | write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg); |
| 30 | |
| 31 | /* lock the write-protect */ |
| 32 | temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG); |
| 33 | temp &= ~SATA_MISC_SUBCLASS_WREN; |
| 34 | pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp); |
| 35 | }; |