| Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <device/device.h> |
| 17 | #include <device/pci.h> |
| 18 | #include <device/pci_ids.h> |
| 19 | #include <device/pci_ops.h> |
| 20 | #include <device/pci_def.h> |
| 21 | #include <amdblocks/sata.h> |
| 22 | #include <soc/southbridge.h> |
| 23 | |
| 24 | void soc_enable_sata_features(struct device *dev) |
| 25 | { |
| 26 | u8 *ahci_ptr; |
| 27 | u32 misc_ctl, cap_cfg; |
| 28 | |
| 29 | u32 temp; |
| 30 | |
| 31 | /* unlock the write-protect */ |
| 32 | misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG); |
| 33 | misc_ctl |= SATA_MISC_SUBCLASS_WREN; |
| 34 | pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl); |
| 35 | |
| 36 | /* set the SATA AHCI mode to allow port expanders */ |
| 37 | ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN( |
| 38 | pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256); |
| 39 | |
| 40 | cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG); |
| 41 | cap_cfg |= SATA_CAPABILITY_SPM; |
| 42 | write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg); |
| 43 | |
| 44 | /* lock the write-protect */ |
| 45 | temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG); |
| 46 | temp &= ~SATA_MISC_SUBCLASS_WREN; |
| 47 | pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp); |
| 48 | }; |