Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; version 2 of |
| 8 | * the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <stddef.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 18 | #include <device/pci_def.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 19 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | f33e835 | 2018-10-24 16:24:44 +0200 | [diff] [blame] | 20 | #include <cpu/intel/speedstep.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 21 | |
| 22 | #include "gm45.h" |
| 23 | |
| 24 | static int sku_freq_index(const gmch_gfx_t sku, const int low_power_mode) |
| 25 | { |
| 26 | if (low_power_mode) |
| 27 | return 1; |
| 28 | switch (sku) { |
| 29 | case GMCH_GM45: |
| 30 | case GMCH_GE45: |
| 31 | case GMCH_GS45: |
| 32 | return 0; |
| 33 | case GMCH_GM47: |
| 34 | return 2; |
| 35 | case GMCH_GM49: |
| 36 | return 3; |
| 37 | default: |
| 38 | return 0; |
| 39 | } |
| 40 | } |
| 41 | static void init_freq_scaling(const gmch_gfx_t sku, const int low_power_mode) |
| 42 | { |
| 43 | int i; |
| 44 | |
| 45 | MCHBAR32(0x11cc) = (MCHBAR32(0x11cc) & ~(0x1f)) | 0x17; |
| 46 | switch (sku) { |
| 47 | case GMCH_GM45: |
| 48 | case GMCH_GE45: |
| 49 | case GMCH_GS45: |
| 50 | case GMCH_GM47: |
| 51 | case GMCH_GM49: |
| 52 | break; |
| 53 | default: |
| 54 | /* No more to be done for the others. */ |
| 55 | return; |
| 56 | } |
| 57 | |
| 58 | static const u32 voltage_mask = |
| 59 | (0x1f << 24) | (0x1f << 16) | (0x1f << 8) | 0x1f; |
| 60 | MCHBAR32(0x1120) = (MCHBAR32(0x1120) & ~voltage_mask) | 0x10111213; |
| 61 | MCHBAR32(0x1124) = (MCHBAR32(0x1124) & ~voltage_mask) | 0x14151617; |
| 62 | MCHBAR32(0x1128) = (MCHBAR32(0x1128) & ~voltage_mask) | 0x18191a1b; |
| 63 | MCHBAR32(0x112c) = (MCHBAR32(0x112c) & ~voltage_mask) | 0x1c1d1e1f; |
| 64 | MCHBAR32(0x1130) = (MCHBAR32(0x1130) & ~voltage_mask) | 0x00010203; |
| 65 | MCHBAR32(0x1134) = (MCHBAR32(0x1134) & ~voltage_mask) | 0x04050607; |
| 66 | MCHBAR32(0x1138) = (MCHBAR32(0x1138) & ~voltage_mask) | 0x08090a0b; |
| 67 | MCHBAR32(0x113c) = (MCHBAR32(0x113c) & ~voltage_mask) | 0x0c0d0e0f; |
| 68 | |
| 69 | /* Program frequencies. */ |
| 70 | static const u32 frequencies_from_sku_vco[][4][8] = { |
| 71 | /* GM45/GE45/GS45_perf */ { |
| 72 | /* VCO 2666 */ { 0xcd, 0xbc, 0x9b, 0x8a, 0x79, 0x78, 0x67, 0x56 }, |
| 73 | /* VCO 3200 */ { 0xcd, 0xac, 0x9b, 0x8a, 0x89, 0x78, 0x67, 0x56 }, |
| 74 | /* VCO 4000 */ { 0xac, 0x9b, 0x9a, 0x89, 0x89, 0x68, 0x56, 0x45 }, |
| 75 | /* VCO 5333 */ { 0xab, 0x9a, 0x79, 0x68, 0x57, 0x56, 0x45, 0x34 }, |
| 76 | }, |
| 77 | /* GS45_low_power */ { |
| 78 | /* VCO 2666 */ { 0xcd, 0x8a }, |
| 79 | /* VCO 3200 */ { 0xcd, 0x89 }, |
| 80 | /* VCO 4000 */ { 0xac, 0x89 }, |
| 81 | /* VCO 5333 */ { 0xab, 0x68 }, |
| 82 | }, |
| 83 | /* GM47 */ { |
| 84 | /* VCO 2666 */ { 0xcd, 0xcd, 0xbc, 0x9b, 0x79, 0x78, 0x67, 0x56 }, |
| 85 | /* VCO 3200 */ { 0xde, 0xcd, 0xac, 0x9b, 0x89, 0x78, 0x67, 0x56 }, |
| 86 | /* VCO 4000 */ { 0xcd, 0xac, 0x9b, 0x9a, 0x89, 0x68, 0x56, 0x45 }, |
| 87 | /* VCO 5333 */ { 0xac, 0xab, 0x9a, 0x79, 0x68, 0x56, 0x45, 0x34 }, |
| 88 | }, |
| 89 | /* GM49 */ { |
| 90 | /* VCO 2666 */ { }, |
| 91 | /* VCO 3200 */ { 0xef, 0xde, 0xcd, 0xac, 0x89, 0x78, 0x67, 0x56 }, |
| 92 | /* VCO 4000 */ { 0xef, 0xde, 0xac, 0x9b, 0x89, 0x68, 0x56, 0x45 }, |
| 93 | /* VCO 5333 */ { 0xce, 0xbd, 0xab, 0x9a, 0x68, 0x57, 0x45, 0x34 }, |
| 94 | }}; |
| 95 | const int sku_index = sku_freq_index(sku, low_power_mode); |
| 96 | const int vco_index = raminit_read_vco_index(); |
| 97 | const int reg_limit = low_power_mode ? 1 : 4; |
| 98 | if (sku == GMCH_GM49) |
| 99 | MCHBAR8(0x1110+3) = 0x1b; |
| 100 | else |
| 101 | MCHBAR8(0x1110+3) = 0x17; |
| 102 | MCHBAR8(0x1110+1) = 0x17; |
| 103 | if (!low_power_mode) { |
| 104 | MCHBAR8(0x1114+3) = 0x17; |
| 105 | MCHBAR8(0x1114+1) = 0x17; |
| 106 | MCHBAR8(0x1118+3) = 0x17; |
| 107 | MCHBAR8(0x1118+1) = 0x17; |
| 108 | MCHBAR8(0x111c+3) = 0x17; |
| 109 | MCHBAR8(0x111c+1) = 0x17; |
| 110 | } |
| 111 | for (i = 0; i < reg_limit; ++i) { |
| 112 | const int mchbar = 0x1110 + (i * 4); |
| 113 | MCHBAR8(mchbar + 2) = frequencies_from_sku_vco |
| 114 | [sku_index][vco_index][i * 2 + 0]; |
| 115 | MCHBAR8(mchbar + 0) = frequencies_from_sku_vco |
| 116 | [sku_index][vco_index][i * 2 + 1]; |
| 117 | } |
| 118 | |
| 119 | if (low_power_mode) { |
| 120 | MCHBAR16(0x1190) = |
| 121 | (MCHBAR16(0x1190) & ~((7 << 8) | (7 << 4) | 7)) | |
| 122 | (1 << 8) | (1 << 4) | 1; |
| 123 | } else { |
| 124 | MCHBAR16(0x1190) = |
| 125 | (MCHBAR16(0x1190) & ~((7 << 8) | (7 << 4))) | 7; |
| 126 | if (sku == GMCH_GS45) /* performance mode */ |
| 127 | MCHBAR32(0x0ffc) &= ~(1 << 31); |
| 128 | } |
| 129 | |
| 130 | MCHBAR16(0x0fc0) |= (1 << 11); |
| 131 | MCHBAR16(0x11b8) = 0x333c; |
| 132 | MCHBAR16(0x11c0 + 2) = 0x0303; |
| 133 | MCHBAR32(0x11c4) = 0x0a030a03; |
| 134 | MCHBAR16(0x1100) = (MCHBAR16(0x1100) & ~(0x1f << 8)) | (3 << 8); |
| 135 | MCHBAR16(0x11b8 + 2) = 0x4000; |
| 136 | } |
| 137 | |
Vladimir Serbinenko | 020dc0e | 2014-08-12 22:50:40 +0200 | [diff] [blame] | 138 | void init_pm(const sysinfo_t *const sysinfo, int do_freq_scaling_cfg) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 139 | { |
| 140 | const stepping_t stepping = sysinfo->stepping; |
| 141 | const fsb_clock_t fsb = sysinfo->selected_timings.fsb_clock; |
| 142 | const mem_clock_t memclk = sysinfo->selected_timings.mem_clock; |
| 143 | |
| 144 | MCHBAR16(0xc14) = 0; |
| 145 | MCHBAR16(0xc20) = 0; |
| 146 | MCHBAR32(0xfc0) = 0x001f00fd; |
| 147 | MCHBAR32(0xfc0) |= 3 << 25; |
| 148 | MCHBAR32(0xfc0) |= 1 << 11; |
| 149 | MCHBAR8(0xfb0) = 3; |
| 150 | MCHBAR8(0xf10) |= 1 << 1; |
| 151 | if (fsb == FSB_CLOCK_667MHz) { |
| 152 | MCHBAR16(0xc3a) = 0xea6; |
| 153 | MCHBAR8(0xc16) = (MCHBAR8(0xc16) & 0x80) | 0x0e; |
| 154 | } else if (fsb == FSB_CLOCK_800MHz) { |
| 155 | MCHBAR16(0xc3a) = 0x1194; |
| 156 | MCHBAR8(0xc16) = (MCHBAR8(0xc16) & 0x80) | 0x10; |
| 157 | } else if (fsb == FSB_CLOCK_1067MHz) { |
| 158 | MCHBAR16(0xc3a) = 0x1777; |
| 159 | MCHBAR8(0xc16) = (MCHBAR8(0xc16) & 0x80) | 0x15; |
| 160 | } |
| 161 | MCHBAR8(0xfb8) = 3; |
| 162 | if (fsb == FSB_CLOCK_667MHz) |
| 163 | MCHBAR16(0xc38) = 0x0ea6; |
| 164 | else if (fsb == FSB_CLOCK_800MHz) |
| 165 | MCHBAR16(0xc38) = 0x1194; |
| 166 | else if (fsb == FSB_CLOCK_1067MHz) |
| 167 | MCHBAR16(0xc38) = 0x1777; |
| 168 | MCHBAR8(0xf10) |= 1 << 5; |
| 169 | MCHBAR16(0xc16) |= 3 << 12; |
| 170 | MCHBAR32(0xf60) = 0x01030419; |
| 171 | if (fsb == FSB_CLOCK_667MHz) { |
| 172 | MCHBAR32(0xf00) = 0x00000600; |
| 173 | MCHBAR32(0xf04) = 0x00001d80; |
| 174 | } else if (fsb == FSB_CLOCK_800MHz) { |
| 175 | MCHBAR32(0xf00) = 0x00000700; |
| 176 | MCHBAR32(0xf04) = 0x00002380; |
| 177 | } else if (fsb == FSB_CLOCK_1067MHz) { |
| 178 | MCHBAR32(0xf00) = 0x00000900; |
| 179 | MCHBAR32(0xf04) = 0x00002e80; |
| 180 | } |
| 181 | MCHBAR16(0xf08) = 0x730f; |
| 182 | if (fsb == FSB_CLOCK_667MHz) |
| 183 | MCHBAR16(0xf0c) = 0x0b96; |
| 184 | else if (fsb == FSB_CLOCK_800MHz) |
| 185 | MCHBAR16(0xf0c) = 0x0c99; |
| 186 | else if (fsb == FSB_CLOCK_1067MHz) |
| 187 | MCHBAR16(0xf0c) = 0x10a4; |
| 188 | MCHBAR32(0xf80) |= 1 << 31; |
| 189 | |
| 190 | MCHBAR32(0x40) = (MCHBAR32(0x40) & ~(0x3f << 24)) | |
| 191 | (sysinfo->cores == 4) ? (1 << 24) : 0; |
| 192 | |
| 193 | MCHBAR32(0x40) &= ~(1 << 19); |
| 194 | MCHBAR32(0x40) |= 1 << 13; |
| 195 | MCHBAR32(0x40) |= 1 << 21; |
| 196 | MCHBAR32(0x40) |= 1 << 9; |
| 197 | if (stepping > STEPPING_B1) { |
| 198 | if (fsb != FSB_CLOCK_1067MHz) { |
| 199 | MCHBAR32(0x70) |= 1 << 30; |
| 200 | } else { |
| 201 | MCHBAR32(0x70) &= ~(1 << 30); |
| 202 | } |
| 203 | } |
| 204 | if (stepping < STEPPING_B1) |
| 205 | MCHBAR32(0x70) |= 1 << 29; |
| 206 | else |
| 207 | MCHBAR32(0x70) &= ~(1 << 29); |
| 208 | if (stepping > STEPPING_B1) { |
| 209 | MCHBAR32(0x70) |= 1 << 28; |
| 210 | MCHBAR32(0x70) |= 1 << 25; |
| 211 | } |
| 212 | if (stepping > STEPPING_B0) { |
| 213 | if (fsb != FSB_CLOCK_667MHz) |
| 214 | MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21)) | (1 << 21); |
| 215 | else |
| 216 | MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21)); |
| 217 | } |
| 218 | if (stepping > STEPPING_B2) |
| 219 | MCHBAR32(0x44) |= 1 << 30; |
| 220 | MCHBAR32(0x44) |= 1 << 31; |
| 221 | if (sysinfo->cores == 2) |
| 222 | MCHBAR32(0x44) |= 1 << 26; |
| 223 | MCHBAR32(0x44) |= 1 << 21; |
| 224 | MCHBAR32(0x44) = (MCHBAR32(0x44) & ~(3 << 24)) | (2 << 24); |
| 225 | MCHBAR32(0x44) |= 1 << 5; |
| 226 | MCHBAR32(0x44) |= 1 << 4; |
| 227 | MCHBAR32(0x90) = (MCHBAR32(0x90) & ~7) | 4; |
| 228 | MCHBAR32(0x94) |= 1 << 29; |
| 229 | MCHBAR32(0x94) |= 1 << 11; |
| 230 | if (stepping < STEPPING_B0) |
| 231 | MCHBAR32(0x94) = (MCHBAR32(0x94) & ~(3 << 19)) | (2 << 19); |
| 232 | if (stepping > STEPPING_B2) |
| 233 | MCHBAR32(0x94) |= 1 << 21; |
| 234 | MCHBAR8(0xb00) &= ~1; |
| 235 | MCHBAR8(0xb00) |= 1 << 7; |
| 236 | if (fsb != FSB_CLOCK_1067MHz) |
| 237 | MCHBAR8(0x75) |= 1 << 6; |
| 238 | else |
| 239 | MCHBAR8(0x75) &= 1 << 1; |
| 240 | MCHBAR8(0x77) |= 3; |
| 241 | if (stepping >= STEPPING_B1) |
| 242 | MCHBAR8(0x77) |= 1 << 2; |
| 243 | if (stepping > STEPPING_B2) |
| 244 | MCHBAR8(0x77) |= 1 << 4; |
| 245 | if (MCHBAR16(0x90) & 0x100) |
| 246 | MCHBAR8(0x90) &= ~(7 << 4); |
| 247 | if (stepping >= STEPPING_B0) |
| 248 | MCHBAR8(0xd0) |= 1 << 1; |
| 249 | MCHBAR8(0xbd8) |= 3 << 2; |
| 250 | if (stepping >= STEPPING_B3) |
| 251 | MCHBAR32(0x70) |= 1 << 0; |
| 252 | MCHBAR32(0x70) |= 1 << 3; |
| 253 | if (stepping >= STEPPING_B0) |
| 254 | MCHBAR32(0x70) &= ~(1 << 16); |
| 255 | else |
| 256 | MCHBAR32(0x70) |= 1 << 16; |
| 257 | if (stepping >= STEPPING_B3) |
| 258 | MCHBAR8(0xc14) |= 1 << 1; |
| 259 | if (stepping >= STEPPING_B1) |
| 260 | MCHBAR16(0xffc) = (MCHBAR16(0xffc) & ~0x7ff) | 0x7c0; |
| 261 | MCHBAR16(0x48) = (MCHBAR16(0x48) & ~(0xff << 2)) | (0xaa << 2); |
| 262 | if (stepping == STEPPING_CONVERSION_A1) { |
| 263 | MCHBAR16(0x40) |= 1 << 12; |
| 264 | MCHBAR32(0x94) |= 3 << 22; |
| 265 | } |
| 266 | |
Elyes HAOUAS | f33e835 | 2018-10-24 16:24:44 +0200 | [diff] [blame] | 267 | const int cpu_supports_super_lfm = |
| 268 | rdmsr(MSR_EXTENDED_CONFIG).lo & (1 << 27); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 269 | if ((stepping >= STEPPING_B0) && cpu_supports_super_lfm) { |
| 270 | MCHBAR16(CLKCFG_MCHBAR) &= ~(1 << 7); |
| 271 | MCHBAR16(CLKCFG_MCHBAR) |= 1 << 14; |
| 272 | } else { |
| 273 | MCHBAR16(CLKCFG_MCHBAR) &= ~(1 << 14); |
| 274 | MCHBAR16(CLKCFG_MCHBAR) |= 1 << 7; |
| 275 | MCHBAR32(0x44) &= ~(1 << 31); /* Was set above. */ |
| 276 | } |
| 277 | |
Vladimir Serbinenko | 020dc0e | 2014-08-12 22:50:40 +0200 | [diff] [blame] | 278 | if ((sysinfo->gfx_type != GMCH_PM45) && do_freq_scaling_cfg && |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 279 | (sysinfo->gfx_type != GMCH_UNKNOWN)) |
| 280 | init_freq_scaling(sysinfo->gfx_type, |
| 281 | sysinfo->gs45_low_power_mode); |
| 282 | |
| 283 | /* This has to be the last write to CLKCFG. */ |
| 284 | if ((fsb == FSB_CLOCK_1067MHz) && (memclk == MEM_CLOCK_667MT)) |
| 285 | MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 17); |
| 286 | } |