blob: 0ceef6a2fd4606b7bcf85651add1583893c9e2bf [file] [log] [blame]
Stefan Reinauer838c5a52010-01-17 14:08:17 +00001##
2## This file is part of the coreboot project.
Stefan Reinauer14e22772010-04-27 06:56:47 +00003##
Stefan Reinauer838c5a52010-01-17 14:08:17 +00004## Copyright (C) 2007-2009 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or
7## modify it under the terms of the GNU General Public License as
8## published by the Free Software Foundation; version 2 of
9## the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
Stefan Reinauer838c5a52010-01-17 14:08:17 +000016
17chip northbridge/intel/i945
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010018 # IGD Displays
19 register "gfx.ndid" = "3"
20 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
Stefan Reinauer838c5a52010-01-17 14:08:17 +000021
Elyes HAOUASb0f19882018-06-09 11:59:00 +020022 device cpu_cluster 0 on
Nico Huber4829af12019-02-27 14:23:18 +010023 chip cpu/intel/socket_m
Elyes HAOUASb0f19882018-06-09 11:59:00 +020024 device lapic 0 on end
25 end
26 end
Stefan Reinauer838c5a52010-01-17 14:08:17 +000027
Arthur Heymans885c2892016-10-03 17:16:48 +020028 register "pci_mmio_size" = "768"
29
Elyes HAOUASb0f19882018-06-09 11:59:00 +020030 device domain 0 on
31 subsystemid 0x4352 0x6886 inherit
32 device pci 00.0 on end # host bridge
Stefan Reinauer838c5a52010-01-17 14:08:17 +000033 # auto detection:
34 #device pci 01.0 off end # i945 PCIe root port
Patrick Georgi2e2a68b2012-05-03 11:34:20 +020035 device pci 02.0 on end # vga controller
36 device pci 02.1 on end # display controller
Stefan Reinauer838c5a52010-01-17 14:08:17 +000037
Elyes HAOUASb0f19882018-06-09 11:59:00 +020038 chip southbridge/intel/i82801gx
Stefan Reinauer838c5a52010-01-17 14:08:17 +000039 register "pirqa_routing" = "0x0b"
40 register "pirqb_routing" = "0x0b"
41 register "pirqc_routing" = "0x0b"
42 register "pirqd_routing" = "0x0b"
43 register "pirqe_routing" = "0x80"
44 register "pirqf_routing" = "0x80"
45 register "pirqg_routing" = "0x0b"
46 register "pirqh_routing" = "0x0b"
47
48 # GPI routing
49 # 0 No effect (default)
50 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
51 # 2 SCI (if corresponding GPIO_EN bit is also set)
52 register "gpi13_routing" = "2"
53 register "gpi8_routing" = "1"
54 register "gpi7_routing" = "2"
55 register "gpe0_en" = "0x20800007"
56
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +020057 register "c3_latency" = "0x23"
58 register "docking_supported" = "1"
59 register "p_cnt_throttling_supported" = "1"
60
Nico Huberae317692019-07-20 17:03:56 +020061 register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
Elyes HAOUASb0f19882018-06-09 11:59:00 +020062 register "ide_enable_primary" = "0x1"
63 register "ide_enable_secondary" = "0x0"
Stefan Reinauer838c5a52010-01-17 14:08:17 +000064
Arthur Heymansd2510992019-01-07 15:30:21 +010065 device pci 1b.0 off end # High Definition Audio
Arthur Heymansb9d25892018-06-15 22:02:28 +020066 device pci 1c.0 on end # PCIe port 1
67 device pci 1c.1 off end # PCIe port 2
68 device pci 1c.2 off end # PCIe port 3
69 device pci 1c.3 on end # PCIe port 4
70 device pci 1c.4 off end # PCIe port 5
71 device pci 1c.5 off end # PCIe port 6
Elyes HAOUASb0f19882018-06-09 11:59:00 +020072 device pci 1d.0 on end # USB UHCI
73 device pci 1d.1 on end # USB UHCI
74 device pci 1d.2 on end # USB UHCI
75 device pci 1d.3 on end # USB UHCI
76 device pci 1d.7 on end # USB2 EHCI
77 device pci 1e.0 on
Stefan Reinauer838c5a52010-01-17 14:08:17 +000078 chip southbridge/ti/pci7420
Elyes HAOUASb0f19882018-06-09 11:59:00 +020079 register "smartcard_enabled" = "0x0"
Stefan Reinauer838c5a52010-01-17 14:08:17 +000080 device pci 3.0 on end
81 device pci 3.1 on end
82 device pci 3.2 on end
83 device pci 3.3 off end # smartcard
84 end
85 end # PCI bridge
Arthur Heymansd2510992019-01-07 15:30:21 +010086 device pci 1e.2 on end # AC'97 Audio
Arthur Heymansb9d25892018-06-15 22:02:28 +020087 device pci 1e.3 off end # AC'97 Modem
Elyes HAOUASb0f19882018-06-09 11:59:00 +020088 device pci 1f.0 on # LPC bridge
89 chip superio/smsc/lpc47n227
Patrick Georgia4700192011-01-27 07:39:38 +000090 device pnp 2e.1 on # Parallel port
91 io 0x60 = 0x378
92 irq 0x70 = 5
Stefan Reinauer838c5a52010-01-17 14:08:17 +000093 end
94 device pnp 2e.2 on # COM1
Elyes HAOUASb0f19882018-06-09 11:59:00 +020095 io 0x60 = 0x3f8
96 irq 0x70 = 4
Stefan Reinauer838c5a52010-01-17 14:08:17 +000097 end
98 device pnp 2e.3 on # COM2
Elyes HAOUASb0f19882018-06-09 11:59:00 +020099 io 0x60 = 0x2f8
100 irq 0x70 = 3
Stefan Reinauer838c5a52010-01-17 14:08:17 +0000101 end
102 device pnp 2e.5 off # Keyboard+Mouse
103 # io 0x60 = 0x60
104 # io 0x62 = 0x64
105 # irq 0x70 = 1
106 # irq 0x72 = 12
107 end
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200108 end
Stefan Reinauer838c5a52010-01-17 14:08:17 +0000109 chip superio/renesas/m3885x
110 device pnp ff.1 on # dummy address
111 end
112 end
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000113 chip ec/acpi
114 end
Stefan Reinauer838c5a52010-01-17 14:08:17 +0000115
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200116 end
Arthur Heymansb9d25892018-06-15 22:02:28 +0200117 device pci 1f.1 off end # IDE
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200118 device pci 1f.2 on end # SATA
119 device pci 1f.3 on end # SMBus
Elyes HAOUASb0f19882018-06-09 11:59:00 +0200120 end
121 end
Stefan Reinauer838c5a52010-01-17 14:08:17 +0000122end