blob: 3fe8b2ae53648da522cc0b43a4cc370c326ed012 [file] [log] [blame]
Stefan Reinauer838c5a52010-01-17 14:08:17 +00001##
2## This file is part of the coreboot project.
Stefan Reinauer14e22772010-04-27 06:56:47 +00003##
Stefan Reinauer838c5a52010-01-17 14:08:17 +00004## Copyright (C) 2007-2009 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or
7## modify it under the terms of the GNU General Public License as
8## published by the Free Software Foundation; version 2 of
9## the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
19## MA 02110-1301 USA
20##
21
22chip northbridge/intel/i945
23
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080024 device cpu_cluster 0 on
Stefan Reinauer838c5a52010-01-17 14:08:17 +000025 chip cpu/intel/socket_mFCPGA478
Patrick Georgi8d313682010-05-05 13:12:42 +000026 device lapic 0 on end
Stefan Reinauer838c5a52010-01-17 14:08:17 +000027 end
28 end
29
Stefan Reinauer4aff4452013-02-12 14:17:15 -080030 device domain 0 on
Sylvain "ythier" Hitier82419412011-03-01 22:02:37 +000031 subsystemid 0x4352 0x6886 inherit
Stefan Reinauer838c5a52010-01-17 14:08:17 +000032 device pci 00.0 on end # host bridge
33 # auto detection:
34 #device pci 01.0 off end # i945 PCIe root port
Patrick Georgi2e2a68b2012-05-03 11:34:20 +020035 device pci 02.0 on end # vga controller
36 device pci 02.1 on end # display controller
Stefan Reinauer838c5a52010-01-17 14:08:17 +000037
38 chip southbridge/intel/i82801gx
39 register "pirqa_routing" = "0x0b"
40 register "pirqb_routing" = "0x0b"
41 register "pirqc_routing" = "0x0b"
42 register "pirqd_routing" = "0x0b"
43 register "pirqe_routing" = "0x80"
44 register "pirqf_routing" = "0x80"
45 register "pirqg_routing" = "0x0b"
46 register "pirqh_routing" = "0x0b"
47
48 # GPI routing
49 # 0 No effect (default)
50 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
51 # 2 SCI (if corresponding GPIO_EN bit is also set)
52 register "gpi13_routing" = "2"
53 register "gpi8_routing" = "1"
54 register "gpi7_routing" = "2"
55 register "gpe0_en" = "0x20800007"
56
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +020057 register "c3_latency" = "0x23"
58 register "docking_supported" = "1"
59 register "p_cnt_throttling_supported" = "1"
60
Stefan Reinauer838c5a52010-01-17 14:08:17 +000061 register "ide_legacy_combined" = "0x1"
62 register "ide_enable_primary" = "0x1"
63 register "ide_enable_secondary" = "0x0"
64 register "sata_ahci" = "0x0"
65
66 device pci 1b.0 on end # High Definition Audio
67 device pci 1c.0 on end # PCIe
68 device pci 1c.1 on end # PCIe
69 device pci 1c.2 on end # PCIe
70 #device pci 1c.3 off end # PCIe port 4
71 #device pci 1c.4 off end # PCIe port 5
72 #device pci 1c.5 off end # PCIe port 6
73 device pci 1d.0 on end # USB UHCI
74 device pci 1d.1 on end # USB UHCI
75 device pci 1d.2 on end # USB UHCI
76 device pci 1d.3 on end # USB UHCI
77 device pci 1d.7 on end # USB2 EHCI
78 device pci 1e.0 on
79 chip southbridge/ti/pci7420
80 register "smartcard_enabled" = "0x0"
81 device pci 3.0 on end
82 device pci 3.1 on end
83 device pci 3.2 on end
84 device pci 3.3 off end # smartcard
85 end
86 end # PCI bridge
Stefan Reinauer14e22772010-04-27 06:56:47 +000087 #device pci 1e.2 off end # AC'97 Audio
Stefan Reinauer838c5a52010-01-17 14:08:17 +000088 #device pci 1e.3 off end # AC'97 Modem
89 device pci 1f.0 on # LPC bridge
90 chip superio/smsc/lpc47n227
Patrick Georgia4700192011-01-27 07:39:38 +000091 device pnp 2e.1 on # Parallel port
92 io 0x60 = 0x378
93 irq 0x70 = 5
Stefan Reinauer838c5a52010-01-17 14:08:17 +000094 end
95 device pnp 2e.2 on # COM1
96 io 0x60 = 0x3f8
97 irq 0x70 = 4
98 end
99 device pnp 2e.3 on # COM2
100 io 0x60 = 0x2f8
101 irq 0x70 = 3
102 end
103 device pnp 2e.5 off # Keyboard+Mouse
104 # io 0x60 = 0x60
105 # io 0x62 = 0x64
106 # irq 0x70 = 1
107 # irq 0x72 = 12
108 end
109 end
110 chip superio/renesas/m3885x
111 device pnp ff.1 on # dummy address
112 end
113 end
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000114 chip ec/acpi
115 end
Stefan Reinauer838c5a52010-01-17 14:08:17 +0000116
117 end
118 #device pci 1f.1 off end # IDE
119 device pci 1f.2 on end # SATA
120 device pci 1f.3 on end # SMBus
121 #device pci 1f.4 off end # Realtek ID Codec
122 end
123 end
124end