Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 2 | |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 3 | #include <assert.h> |
| 4 | #include <bootstate.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 6 | #include <cpu/cpu.h> |
| 7 | #include <cpu/x86/mtrr.h> |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 8 | #include <cpu/x86/mp.h> |
| 9 | #include <cpu/intel/microcode.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 10 | #include <intelblocks/cfg.h> |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 11 | #include <intelblocks/cpulib.h> |
| 12 | #include <intelblocks/fast_spi.h> |
| 13 | #include <intelblocks/mp_init.h> |
| 14 | #include <intelblocks/msr.h> |
| 15 | #include <soc/cpu.h> |
| 16 | |
Subrata Banik | bdea352 | 2022-05-31 23:36:59 +0530 | [diff] [blame] | 17 | static void initialize_microcode(void) |
| 18 | { |
| 19 | const void *microcode_patch = intel_microcode_find(); |
| 20 | intel_microcode_load_unlocked(microcode_patch); |
| 21 | } |
| 22 | |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 23 | static void init_one_cpu(struct device *dev) |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 24 | { |
Pratik Prajapati | 9cd6a26 | 2017-08-14 13:57:46 -0700 | [diff] [blame] | 25 | soc_core_init(dev); |
Patrick Rudolph | 3fa23b8 | 2021-01-25 09:42:08 +0100 | [diff] [blame] | 26 | |
Subrata Banik | bdea352 | 2022-05-31 23:36:59 +0530 | [diff] [blame] | 27 | initialize_microcode(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 28 | } |
| 29 | |
| 30 | static struct device_operations cpu_dev_ops = { |
| 31 | .init = init_one_cpu, |
| 32 | }; |
| 33 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 34 | static const struct cpu_device_id cpu_table[] = { |
Wonkyu Kim | 9f40107 | 2020-11-13 15:16:32 -0800 | [diff] [blame] | 35 | { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1}, |
| 36 | { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2}, |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 37 | { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0 }, |
| 38 | { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 }, |
| 39 | { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 }, |
| 40 | { X86_VENDOR_INTEL, CPUID_SKYLAKE_HR0 }, |
| 41 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_G0 }, |
| 42 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_H0 }, |
| 43 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_Y0 }, |
| 44 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_HA0 }, |
| 45 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_HB0 }, |
Barnali Sarkar | cc22b73 | 2017-08-07 18:44:02 +0530 | [diff] [blame] | 46 | { X86_VENDOR_INTEL, CPUID_CANNONLAKE_A0 }, |
| 47 | { X86_VENDOR_INTEL, CPUID_CANNONLAKE_B0 }, |
| 48 | { X86_VENDOR_INTEL, CPUID_CANNONLAKE_C0 }, |
Lijian Zhao | e987228 | 2018-01-21 21:05:54 -0800 | [diff] [blame] | 49 | { X86_VENDOR_INTEL, CPUID_CANNONLAKE_D0 }, |
Barnali Sarkar | cc22b73 | 2017-08-07 18:44:02 +0530 | [diff] [blame] | 50 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 }, |
| 51 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 }, |
Mario Scheithauer | 545593d | 2017-10-24 17:41:19 +0200 | [diff] [blame] | 52 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, |
Barnali Sarkar | cc22b73 | 2017-08-07 18:44:02 +0530 | [diff] [blame] | 53 | { X86_VENDOR_INTEL, CPUID_GLK_A0 }, |
| 54 | { X86_VENDOR_INTEL, CPUID_GLK_B0 }, |
John Zhao | 7528f83 | 2019-05-10 10:51:52 -0700 | [diff] [blame] | 55 | { X86_VENDOR_INTEL, CPUID_GLK_R0 }, |
Lijian Zhao | 34745f6 | 2019-02-15 05:36:50 -0800 | [diff] [blame] | 56 | { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0 }, |
Krzysztof Sywula | cdeb414 | 2018-07-16 05:25:34 -0700 | [diff] [blame] | 57 | { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, |
Maulik | fc19ab5 | 2018-01-05 22:40:35 +0530 | [diff] [blame] | 58 | { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, |
Felix Singer | d298ffe | 2019-07-28 13:27:11 +0200 | [diff] [blame] | 59 | { X86_VENDOR_INTEL, CPUID_COFFEELAKE_B0 }, |
Lean Sheng Tan | 38c3ff7 | 2019-05-27 13:06:35 +0800 | [diff] [blame] | 60 | { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 }, |
| 61 | { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 }, |
Ronak Kanabar | 128bb2a | 2019-01-29 19:52:53 +0530 | [diff] [blame] | 62 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, |
| 63 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0 }, |
Gaggery Tsai | fdcc9ab | 2019-11-04 20:49:10 -0800 | [diff] [blame] | 64 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G0 }, |
| 65 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G1 }, |
Ronak Kanabar | 128bb2a | 2019-01-29 19:52:53 +0530 | [diff] [blame] | 66 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0 }, |
Jeremy Soller | c5d0761 | 2022-07-26 08:18:38 -0600 | [diff] [blame] | 67 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P1 }, |
| 68 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0 }, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame] | 69 | { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0 }, |
Jamie Ryu | 5131c6f | 2020-05-18 10:13:31 -0700 | [diff] [blame] | 70 | { X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0 }, |
Jeremy Soller | 49759f6 | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 71 | { X86_VENDOR_INTEL, CPUID_TIGERLAKE_R0 }, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 72 | { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0 }, |
Tan, Lean Sheng | 7337bdc | 2020-08-25 08:24:47 -0700 | [diff] [blame] | 73 | { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0 }, |
Subrata Banik | f672f7f | 2020-08-03 14:29:25 +0530 | [diff] [blame] | 74 | { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0 }, |
| 75 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0 }, |
Lean Sheng Tan | 9e78dd1 | 2022-04-01 12:03:51 +0200 | [diff] [blame] | 76 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0 }, |
| 77 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0 }, |
Lean Sheng Tan | 311ddf3 | 2022-04-01 18:36:11 +0200 | [diff] [blame] | 78 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_L0 }, |
Lean Sheng Tan | 9e78dd1 | 2022-04-01 12:03:51 +0200 | [diff] [blame] | 79 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 }, |
| 80 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 }, |
Paul Menzel | bdaff7e | 2022-01-08 10:21:59 +0100 | [diff] [blame] | 81 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 }, |
Bora Guvendik | a15b25f | 2022-02-28 14:43:49 -0800 | [diff] [blame] | 82 | { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_J0 }, |
zhixingma | 529a64b | 2022-06-13 15:06:27 -0700 | [diff] [blame] | 83 | { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_Q0 }, |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 84 | { 0, 0 }, |
| 85 | }; |
| 86 | |
| 87 | static const struct cpu_driver driver __cpu_driver = { |
| 88 | .ops = &cpu_dev_ops, |
| 89 | .id_table = cpu_table, |
| 90 | }; |
| 91 | |
| 92 | /* |
| 93 | * MP Init callback function to Find CPU Topology. This function is common |
| 94 | * among all SOCs and thus its in Common CPU block. |
| 95 | */ |
| 96 | int get_cpu_count(void) |
| 97 | { |
| 98 | unsigned int num_virt_cores, num_phys_cores; |
| 99 | |
| 100 | cpu_read_topology(&num_phys_cores, &num_virt_cores); |
| 101 | |
| 102 | printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n", |
| 103 | num_phys_cores, num_virt_cores); |
| 104 | |
| 105 | return num_virt_cores; |
| 106 | } |
| 107 | |
| 108 | /* |
| 109 | * MP Init callback function(get_microcode_info) to find the Microcode at |
| 110 | * Pre MP Init phase. This function is common among all SOCs and thus its in |
| 111 | * Common CPU block. |
| 112 | * This function also fills in the microcode patch (in *microcode), and also |
| 113 | * sets the argument *parallel to 1, which allows microcode loading in all |
| 114 | * APs to occur in parallel during MP Init. |
| 115 | */ |
| 116 | void get_microcode_info(const void **microcode, int *parallel) |
| 117 | { |
Patrick Rudolph | 3fa23b8 | 2021-01-25 09:42:08 +0100 | [diff] [blame] | 118 | *microcode = intel_microcode_find(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 119 | *parallel = 1; |
| 120 | } |
| 121 | |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 122 | /* |
| 123 | * Perform BSP and AP initialization |
| 124 | * This function can be called in below cases: |
| 125 | * 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude |
| 126 | * this call if user has selected USE_INTEL_FSP_MP_INIT). |
| 127 | * 2. coreboot would like to take APs control back after FSP-S has done with MP |
| 128 | * initialization based on user select USE_INTEL_FSP_MP_INIT. |
MAULIK V VAGHELA | 3c0ecd5 | 2021-08-02 13:11:46 +0530 | [diff] [blame] | 129 | * |
| 130 | * This function would use cpu_cluster as a device and APIC device as a linked list to |
| 131 | * the cpu cluster. This function adds a node in case the mainboard doesn't have a lapic id |
| 132 | * hardcoded in devicetree, and then fills with the actual BSP APIC ID. |
| 133 | * This allows coreboot to dynamically detect the LAPIC ID of BSP. |
| 134 | * In case the mainboard has an APIC ID defined in devicetree, a link will be present and |
| 135 | * creation of the new node will be skipped. This node will have the APIC ID defined |
| 136 | * in devicetree. |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 137 | */ |
| 138 | void init_cpus(void) |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 139 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 140 | struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 141 | assert(dev != NULL); |
| 142 | |
MAULIK V VAGHELA | 3c0ecd5 | 2021-08-02 13:11:46 +0530 | [diff] [blame] | 143 | /* In case link to APIC device is not found, create the one */ |
| 144 | if (!dev->link_list) |
| 145 | add_more_links(dev, 1); |
| 146 | |
| 147 | soc_init_cpus(dev->link_list); |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | static void coreboot_init_cpus(void *unused) |
| 151 | { |
Subrata Banik | cf32fd1 | 2018-12-19 18:02:17 +0530 | [diff] [blame] | 152 | if (CONFIG(USE_INTEL_FSP_MP_INIT)) |
Subrata Banik | f699c14 | 2018-06-08 17:57:37 +0530 | [diff] [blame] | 153 | return; |
| 154 | |
Subrata Banik | bdea352 | 2022-05-31 23:36:59 +0530 | [diff] [blame] | 155 | initialize_microcode(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 156 | |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 157 | init_cpus(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 158 | } |
| 159 | |
Subrata Banik | 73ad818 | 2022-03-15 18:29:33 +0530 | [diff] [blame] | 160 | static void post_cpus_add_romcache(void) |
| 161 | { |
| 162 | if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) |
| 163 | return; |
| 164 | |
| 165 | fast_spi_cache_bios_region(); |
| 166 | } |
| 167 | |
Subrata Banik | 3337497 | 2018-04-24 13:45:30 +0530 | [diff] [blame] | 168 | static void wrapper_x86_setup_mtrrs(void *unused) |
| 169 | { |
| 170 | x86_setup_mtrrs_with_detect(); |
| 171 | } |
| 172 | |
Subrata Banik | e43adb6 | 2022-05-31 23:28:57 +0530 | [diff] [blame] | 173 | static void wrapper_set_bios_done(void *unused) |
| 174 | { |
| 175 | cpu_soc_bios_done(); |
| 176 | } |
| 177 | |
Subrata Banik | 861ec01 | 2022-06-16 00:02:39 +0530 | [diff] [blame] | 178 | static void wrapper_init_core_prmrr(void *unused) |
| 179 | { |
| 180 | init_core_prmrr(); |
| 181 | } |
| 182 | |
Subrata Banik | e43adb6 | 2022-05-31 23:28:57 +0530 | [diff] [blame] | 183 | void before_post_cpus_init(void) |
| 184 | { |
Subrata Banik | 957609d | 2022-06-16 20:25:08 +0530 | [diff] [blame] | 185 | /* |
| 186 | * Ensure all APs finish the task and continue if coreboot decides to |
| 187 | * perform multiprocessor initialization using native coreboot drivers |
| 188 | * instead using FSP MP PPI implementation. |
| 189 | * |
| 190 | * Ignore if USE_COREBOOT_MP_INIT is not enabled. |
| 191 | */ |
| 192 | if (!CONFIG(USE_COREBOOT_MP_INIT)) |
| 193 | return; |
| 194 | |
Subrata Banik | 5a9b7aa | 2022-08-12 17:14:43 +0530 | [diff] [blame] | 195 | if (mp_run_on_all_cpus(wrapper_init_core_prmrr, NULL) != CB_SUCCESS) |
Subrata Banik | 861ec01 | 2022-06-16 00:02:39 +0530 | [diff] [blame] | 196 | printk(BIOS_ERR, "core PRMRR sync failure\n"); |
| 197 | |
Subrata Banik | 5a9b7aa | 2022-08-12 17:14:43 +0530 | [diff] [blame] | 198 | if (mp_run_on_all_cpus(wrapper_set_bios_done, NULL) != CB_SUCCESS) |
Subrata Banik | e43adb6 | 2022-05-31 23:28:57 +0530 | [diff] [blame] | 199 | printk(BIOS_ERR, "Set BIOS Done failure\n"); |
Subrata Banik | f4fe21d | 2022-05-31 23:43:36 +0530 | [diff] [blame] | 200 | |
Subrata Banik | 46265ab | 2022-06-15 21:39:06 +0530 | [diff] [blame] | 201 | intel_reload_microcode(); |
Subrata Banik | e43adb6 | 2022-05-31 23:28:57 +0530 | [diff] [blame] | 202 | } |
| 203 | |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 204 | /* Ensure to re-program all MTRRs based on DRAM resource settings */ |
| 205 | static void post_cpus_init(void *unused) |
| 206 | { |
Kane Chen | 2e96eeb | 2022-04-12 09:12:59 +0800 | [diff] [blame] | 207 | /* Ensure all APs finish the task and continue */ |
| 208 | if (mp_run_on_all_cpus_synchronously(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS) |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 209 | printk(BIOS_ERR, "MTRR programming failure\n"); |
| 210 | |
Subrata Banik | 73ad818 | 2022-03-15 18:29:33 +0530 | [diff] [blame] | 211 | post_cpus_add_romcache(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 212 | x86_mtrr_check(); |
| 213 | } |
| 214 | |
| 215 | /* Do CPU MP Init before FSP Silicon Init */ |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 216 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, coreboot_init_cpus, NULL); |
Barnali Sarkar | f43adf0 | 2017-12-27 13:48:58 +0530 | [diff] [blame] | 217 | BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL); |
| 218 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, post_cpus_init, NULL); |