| Felix Held | c9737c5c | 2021-09-23 17:16:32 +0200 | [diff] [blame] | 1 | config SOC_AMD_PI |
| Richard Spiegel | 19f67a3 | 2017-12-08 18:16:02 -0700 | [diff] [blame] | 2 | bool |
| Felix Held | c0982ab | 2021-09-23 15:28:51 +0200 | [diff] [blame] | 3 | depends on SOC_AMD_COMMON_BLOCK_ACPI |
| 4 | select CACHE_MRC_SETTINGS |
| Raul E Rangel | 80d042c | 2018-03-20 12:47:46 -0600 | [diff] [blame] | 5 | select HAVE_DEBUG_RAM_SETUP |
| Felix Held | c0982ab | 2021-09-23 15:28:51 +0200 | [diff] [blame] | 6 | select MRC_WRITE_NV_LATE |
| Richard Spiegel | 19f67a3 | 2017-12-08 18:16:02 -0700 | [diff] [blame] | 7 | help |
| Felix Held | befec1e | 2020-11-06 00:26:03 +0100 | [diff] [blame] | 8 | This option builds functions that interface AMD's AGESA reference |
| Felix Held | c0982ab | 2021-09-23 15:28:51 +0200 | [diff] [blame] | 9 | code packaged in the binaryPI form and S3-related functionality. |
| Marshall Dawson | 10b52e0 | 2018-05-07 08:51:04 -0600 | [diff] [blame] | 10 | |
| Felix Held | c9737c5c | 2021-09-23 17:16:32 +0200 | [diff] [blame] | 11 | if SOC_AMD_PI |
| Marshall Dawson | 10b52e0 | 2018-05-07 08:51:04 -0600 | [diff] [blame] | 12 | |
| Marshall Dawson | c150a57 | 2018-04-30 17:59:27 -0600 | [diff] [blame] | 13 | config PI_AGESA_CAR_HEAP_BASE |
| 14 | hex |
| 15 | default 0x400000 |
| 16 | help |
| 17 | The AGESA PI blob may be built to allow an optional callout for |
| 18 | AgesaHeapRebase. If AGESA calls AgesaHeapRebase, this option |
| 19 | determines the location of the heap prior to DRAM availability. |
| 20 | |
| Marshall Dawson | 10b52e0 | 2018-05-07 08:51:04 -0600 | [diff] [blame] | 21 | config PI_AGESA_TEMP_RAM_BASE |
| 22 | hex |
| 23 | default 0x100000 |
| 24 | help |
| 25 | During a boot from S5, AGESA copies its CAR-based heap to a temporary |
| 26 | location in DRAM. Once coreboot has established cbmem, the heap |
| 27 | is moved again. This symbol determines the temporary location for |
| 28 | the heap. |
| 29 | |
| 30 | config PI_AGESA_HEAP_SIZE |
| 31 | hex |
| 32 | default 0x20000 |
| 33 | help |
| 34 | This option determines the amount of space allowed for AGESA heap |
| 35 | prior to DRAM availability. |
| 36 | |
| Felix Held | c9737c5c | 2021-09-23 17:16:32 +0200 | [diff] [blame] | 37 | endif # SOC_AMD_PI |