| config SOC_AMD_PI |
| bool |
| depends on SOC_AMD_COMMON_BLOCK_ACPI |
| select CACHE_MRC_SETTINGS |
| select HAVE_DEBUG_RAM_SETUP |
| select MRC_WRITE_NV_LATE |
| help |
| This option builds functions that interface AMD's AGESA reference |
| code packaged in the binaryPI form and S3-related functionality. |
| |
| if SOC_AMD_PI |
| |
| config PI_AGESA_CAR_HEAP_BASE |
| hex |
| default 0x400000 |
| help |
| The AGESA PI blob may be built to allow an optional callout for |
| AgesaHeapRebase. If AGESA calls AgesaHeapRebase, this option |
| determines the location of the heap prior to DRAM availability. |
| |
| config PI_AGESA_TEMP_RAM_BASE |
| hex |
| default 0x100000 |
| help |
| During a boot from S5, AGESA copies its CAR-based heap to a temporary |
| location in DRAM. Once coreboot has established cbmem, the heap |
| is moved again. This symbol determines the temporary location for |
| the heap. |
| |
| config PI_AGESA_HEAP_SIZE |
| hex |
| default 0x20000 |
| help |
| This option determines the amount of space allowed for AGESA heap |
| prior to DRAM availability. |
| |
| endif # SOC_AMD_PI |