Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 2 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
Dinesh Gehlot | 6fecff2 | 2023-01-17 06:02:16 +0000 | [diff] [blame] | 6 | #include <gpio.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 7 | #include <intelblocks/cfg.h> |
Marc Jones | 31ed885 | 2021-01-15 13:29:14 -0700 | [diff] [blame] | 8 | #include <soc/acpi.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 9 | #include <soc/irq.h> |
Dinesh Gehlot | 6fecff2 | 2023-01-17 06:02:16 +0000 | [diff] [blame] | 10 | #include <stdint.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 11 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 12 | struct soc_intel_xeon_sp_skx_config { |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 13 | /* Common struct containing soc config data required by common code */ |
| 14 | struct soc_intel_common_config common_soc_config; |
| 15 | |
| 16 | /** |
| 17 | * Interrupt Routing configuration |
| 18 | * If bit7 is 1, the interrupt is disabled. |
| 19 | */ |
| 20 | uint8_t pirqa_routing; |
| 21 | uint8_t pirqb_routing; |
| 22 | uint8_t pirqc_routing; |
| 23 | uint8_t pirqd_routing; |
| 24 | uint8_t pirqe_routing; |
| 25 | uint8_t pirqf_routing; |
| 26 | uint8_t pirqg_routing; |
| 27 | uint8_t pirqh_routing; |
| 28 | |
| 29 | /** |
| 30 | * Device Interrupt Routing configuration |
| 31 | * Interrupt Pin x Route. |
| 32 | * 0h = PIRQA# |
| 33 | * 1h = PIRQB# |
| 34 | * 2h = PIRQC# |
| 35 | * 3h = PIRQD# |
| 36 | * 4h = PIRQE# |
| 37 | * 5h = PIRQF# |
| 38 | * 6h = PIRQG# |
| 39 | * 7h = PIRQH# |
| 40 | */ |
Rocky Phagura | cced346 | 2020-06-11 11:18:02 -0700 | [diff] [blame] | 41 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 42 | uint16_t ir00_routing; |
| 43 | uint16_t ir01_routing; |
| 44 | uint16_t ir02_routing; |
| 45 | uint16_t ir03_routing; |
| 46 | uint16_t ir04_routing; |
| 47 | |
| 48 | /** |
| 49 | * Device Interrupt Polarity Control |
| 50 | * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC |
| 51 | * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC |
| 52 | * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC |
| 53 | * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC |
| 54 | */ |
| 55 | uint32_t ipc0; |
| 56 | uint32_t ipc1; |
| 57 | uint32_t ipc2; |
| 58 | uint32_t ipc3; |
| 59 | |
| 60 | uint64_t turbo_ratio_limit; |
| 61 | uint64_t turbo_ratio_limit_cores; |
| 62 | |
| 63 | uint32_t pstate_req_ratio; |
| 64 | |
| 65 | uint32_t vtd_support; |
| 66 | uint32_t coherency_support; |
| 67 | uint32_t ats_support; |
Johnny Lin | ebb7f54 | 2020-02-19 15:52:45 +0800 | [diff] [blame] | 68 | |
| 69 | /* Generic IO decode ranges */ |
| 70 | uint32_t gen1_dec; |
| 71 | uint32_t gen2_dec; |
| 72 | uint32_t gen3_dec; |
| 73 | uint32_t gen4_dec; |
Sumeet R Pawnikar | 360684b | 2020-06-18 15:56:11 +0530 | [diff] [blame] | 74 | |
| 75 | /* TCC activation offset */ |
| 76 | uint32_t tcc_offset; |
Marc Jones | 31ed885 | 2021-01-15 13:29:14 -0700 | [diff] [blame] | 77 | |
| 78 | enum acpi_cstate_mode cstate_states; |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 79 | }; |
| 80 | |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 81 | typedef struct soc_intel_xeon_sp_skx_config config_t; |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 82 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 83 | #endif |