blob: 1380cd16cff2e9049663c0a9b7f7c0ddd17f5376 [file] [log] [blame]
Patrick Georgi02363b52020-05-05 20:48:50 +02001/* This file is part of the coreboot project. */
Patrick Georgiac959032020-05-05 22:49:26 +02002/* SPDX-License-Identifier: GPL-2.0-or-later */
Tristan Corrick44095c12018-12-22 00:04:18 +13003
4#include <console/console.h>
5#include <device/device.h>
Tristan Corrick44095c12018-12-22 00:04:18 +13006#include <option.h>
7#include <stdint.h>
8#include <types.h>
9
10/*
11 * Hiding the AST2400 might be desirable to reduce attack surface.
12 *
13 * The PCIe root port that the AST2400 is on is disabled, but the
14 * AST2400 itself likely remains in an enabled state.
15 *
16 * The AST2400 is also attached to the LPC. That interface does not get
17 * disabled.
18 */
19static void hide_ast2400(void)
20{
Elyes HAOUASd2abe932019-01-23 14:18:34 +010021 struct device *dev = pcidev_on_root(0x1c, 0);
Tristan Corrick44095c12018-12-22 00:04:18 +130022 if (!dev)
23 return;
24
25 /*
26 * Marking this device as disabled means that the southbridge code
27 * will properly disable the root port when it configures it later.
28 */
29 dev->enabled = 0;
30 printk(BIOS_INFO, "The AST2400 is now set to be hidden.\n");
31}
32
33static void mainboard_enable(struct device *dev)
34{
35 u8 hide = 0;
36
37 if (get_option(&hide, "hide_ast2400") == CB_SUCCESS && hide)
38 hide_ast2400();
39}
40
41struct chip_operations mainboard_ops = {
42 CHIP_NAME("X10SLM+-F")
43 .enable_dev = mainboard_enable,
44};