blob: 9fbbc3821e23876826d910d969830bd2b4439449 [file] [log] [blame]
Patrick Georgi02363b52020-05-05 20:48:50 +02001/* This file is part of the coreboot project. */
Patrick Georgiac959032020-05-05 22:49:26 +02002/* SPDX-License-Identifier: GPL-2.0-or-later */
Julien Viard de Galbert4f136402018-02-16 14:40:53 +01003
Julien Viard de Galbert4f136402018-02-16 14:40:53 +01004#include "gpio.h"
Julien Viard de Galbert4f136402018-02-16 14:40:53 +01005#include <console/console.h>
6#include <fsp/api.h>
7#include <fsp/soc_binding.h>
Julien Viard de Galbert0e755d42018-03-07 15:48:54 +01008#include "bmcinfo.h"
Julien Viard de Galbert4f136402018-02-16 14:40:53 +01009
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010010void mainboard_config_gpios(void);
11void mainboard_memory_init_params(FSPM_UPD *mupd);
12
13/*
14* Configure GPIO depend on platform
15*/
16void mainboard_config_gpios(void)
17{
18 size_t num;
Julien Viard de Galbertf729cd02018-03-29 11:31:17 +020019 const struct pad_config *table;
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010020
Julien Viard de Galbert0e755d42018-03-07 15:48:54 +010021 printk(BIOS_SPEW, "Board Serial: %s.\n", bmcinfo_serial());
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010022 /* Configure pads prior to SiliconInit() in case there's any
23 * dependencies during hardware initialization.
24 */
Julien Viard de Galbert5a2c7962018-02-13 23:19:08 +010025 table = tagada_gpio_config;
26 num = ARRAY_SIZE(tagada_gpio_config);
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010027
28 if ((!table) || (!num)) {
29 printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n");
30 return;
31 }
32
33 printk(BIOS_INFO, "GPIO table: 0x%x, entry num: 0x%x!\n",
34 (uint32_t)table, (uint32_t)num);
Julien Viard de Galbertf729cd02018-03-29 11:31:17 +020035 gpio_configure_pads(table, num);
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010036}
37
38void mainboard_memory_init_params(FSPM_UPD *mupd)
39{
Julien Viard de Galbert0e755d42018-03-07 15:48:54 +010040 mupd->FspmConfig.PcdFspDebugPrintErrorLevel =
41 bmcinfo_fsp_verbosity_level();
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010042
Julien Viard de Galbertd5a192852018-02-13 22:05:26 +010043 // Enable Rmt and Fast Boot by default, RMT will be run only on first
44 // boot or when dimms change
45 mupd->FspmConfig.PcdMrcRmtSupport = 1;
46 mupd->FspmConfig.PcdFastBoot = 1;
Julien Viard de Galbert4f136402018-02-16 14:40:53 +010047}