Patrick Georgi | 02363b5 | 2020-05-05 20:48:50 +0200 | [diff] [blame] | 1 | /* This file is part of the coreboot project. */ |
Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame^] | 2 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Nicola Corna | 1bea5b7 | 2017-03-03 18:04:48 +0100 | [diff] [blame] | 3 | |
| 4 | #include <stdint.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Nicola Corna | 1bea5b7 | 2017-03-03 18:04:48 +0100 | [diff] [blame] | 6 | #include <device/pci_def.h> |
Elyes HAOUAS | 4ad1446 | 2018-06-16 18:29:33 +0200 | [diff] [blame] | 7 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 8 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 9 | #include <southbridge/intel/bd82x6x/pch.h> |
| 10 | |
Arthur Heymans | 2b28a16 | 2019-11-12 17:21:08 +0100 | [diff] [blame] | 11 | void mainboard_pch_lpc_setup(void) |
Nicola Corna | 1bea5b7 | 2017-03-03 18:04:48 +0100 | [diff] [blame] | 12 | { |
Nicola Corna | 1bea5b7 | 2017-03-03 18:04:48 +0100 | [diff] [blame] | 13 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); |
| 14 | } |
| 15 | |
Nicola Corna | 1bea5b7 | 2017-03-03 18:04:48 +0100 | [diff] [blame] | 16 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 17 | { 1, 0, 0 }, |
| 18 | { 1, 0, 0 }, |
| 19 | { 1, 0, 1 }, |
| 20 | { 1, 0, 1 }, |
| 21 | { 1, 0, 2 }, |
| 22 | { 1, 0, 2 }, |
| 23 | { 1, 0, 3 }, |
| 24 | { 1, 0, 3 }, |
| 25 | { 1, 0, 4 }, |
| 26 | { 1, 0, 4 }, |
| 27 | { 1, 0, 6 }, |
| 28 | { 1, 0, 5 }, |
| 29 | { 1, 0, 5 }, |
| 30 | { 1, 0, 6 }, |
| 31 | }; |
| 32 | |
Nicola Corna | 1bea5b7 | 2017-03-03 18:04:48 +0100 | [diff] [blame] | 33 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 34 | { |
| 35 | read_spd(&spd[0], 0x50, id_only); |
| 36 | read_spd(&spd[2], 0x51, id_only); |
| 37 | } |