| Patrick Georgi | 02363b5 | 2020-05-05 20:48:50 +0200 | [diff] [blame] | 1 | /* This file is part of the coreboot project. */ |
| Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame^] | 2 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Nitheesh Sekar | 69cc491 | 2019-03-27 13:14:02 +0530 | [diff] [blame] | 3 | |
| 4 | #include <arch/stages.h> |
| 5 | #include <soc/usb.h> |
| 6 | |
| 7 | static void prepare_usb(void) |
| 8 | { |
| 9 | /* |
| 10 | * Do DWC3 core and phy reset. Kick these resets off early |
| 11 | * so they get atleast 1msec to settle. |
| 12 | */ |
| 13 | reset_usb(HSUSB_HS_PORT_1); |
| 14 | } |
| 15 | |
| 16 | void platform_romstage_main(void) |
| 17 | { |
| 18 | prepare_usb(); |
| 19 | } |