| Nitheesh Sekar | 69cc491 | 2019-03-27 13:14:02 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2018, The Linux Foundation. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 and |
| 8 | * only version 2 as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/stages.h> |
| 17 | #include <soc/usb.h> |
| 18 | |
| 19 | static void prepare_usb(void) |
| 20 | { |
| 21 | /* |
| 22 | * Do DWC3 core and phy reset. Kick these resets off early |
| 23 | * so they get atleast 1msec to settle. |
| 24 | */ |
| 25 | reset_usb(HSUSB_HS_PORT_1); |
| 26 | } |
| 27 | |
| 28 | void platform_romstage_main(void) |
| 29 | { |
| 30 | prepare_usb(); |
| 31 | } |