Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | // Use simple device model for this file even in ramstage |
| 17 | #define __SIMPLE_DEVICE__ |
| 18 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 19 | #include <device/pci_ops.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 20 | #include <arch/cpu.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 21 | #include <cbmem.h> |
| 22 | #include "i945.h" |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 23 | #include <console/console.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 24 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 25 | #include <cpu/x86/mtrr.h> |
| 26 | #include <program_loading.h> |
Arthur Heymans | cf3076e | 2018-04-10 12:57:42 +0200 | [diff] [blame] | 27 | #include <cpu/intel/smm/gen1/smi.h> |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame^] | 28 | #include <stdint.h> |
| 29 | #include <stage_cache.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 30 | |
Arthur Heymans | f6d1477 | 2018-01-26 11:50:04 +0100 | [diff] [blame] | 31 | /* Decodes TSEG region size to bytes. */ |
| 32 | u32 decode_tseg_size(const u8 esmramc) |
| 33 | { |
| 34 | if (!(esmramc & 1)) |
| 35 | return 0; |
| 36 | switch ((esmramc >> 1) & 3) { |
| 37 | case 0: |
| 38 | return 1 << 20; |
| 39 | case 1: |
| 40 | return 2 << 20; |
| 41 | case 2: |
| 42 | return 8 << 20; |
| 43 | case 3: |
| 44 | default: |
| 45 | die("Bad TSEG setting.\n"); |
| 46 | } |
| 47 | } |
| 48 | |
Arthur Heymans | cf3076e | 2018-04-10 12:57:42 +0200 | [diff] [blame] | 49 | u32 northbridge_get_tseg_base(void) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 50 | { |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 51 | uintptr_t tom; |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 52 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 53 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 54 | /* IGD enabled, get top of Memory from BSM register */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 55 | tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); |
| 56 | else |
| 57 | tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 58 | |
Arthur Heymans | f6d1477 | 2018-01-26 11:50:04 +0100 | [diff] [blame] | 59 | /* subsctract TSEG size */ |
| 60 | tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 61 | return tom; |
| 62 | } |
| 63 | |
Arthur Heymans | cf3076e | 2018-04-10 12:57:42 +0200 | [diff] [blame] | 64 | u32 northbridge_get_tseg_size(void) |
| 65 | { |
| 66 | const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); |
| 67 | return decode_tseg_size(esmramc); |
| 68 | } |
| 69 | |
| 70 | /* |
| 71 | * Depending of UMA and TSEG configuration, TSEG might start at any |
Elyes HAOUAS | 64f6b71 | 2018-08-07 12:16:56 +0200 | [diff] [blame] | 72 | * 1 MiB alignment. As this may cause very greedy MTRR setup, push |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 73 | * CBMEM top downwards to 4 MiB boundary. |
| 74 | */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 75 | void *cbmem_top(void) |
| 76 | { |
Arthur Heymans | cf3076e | 2018-04-10 12:57:42 +0200 | [diff] [blame] | 77 | uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); |
Kyösti Mälkki | 811932a | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 78 | return (void *) top_of_ram; |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 79 | } |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 80 | |
| 81 | /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ |
| 82 | u32 decode_igd_memory_size(const u32 gms) |
| 83 | { |
| 84 | static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, |
| 85 | 48, 64 }; |
| 86 | |
Jacob Garber | f74f6cb | 2019-04-08 17:54:35 -0600 | [diff] [blame] | 87 | if (gms >= ARRAY_SIZE(ggc2uma)) |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 88 | die("Bad Graphics Mode Select (GMS) setting.\n"); |
| 89 | |
| 90 | return ggc2uma[gms] << 10; |
| 91 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 92 | |
Kyösti Mälkki | aba8fb1 | 2019-08-02 06:11:28 +0300 | [diff] [blame^] | 93 | void stage_cache_external_region(void **base, size_t *size) |
| 94 | { |
| 95 | /* |
| 96 | * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. |
| 97 | * The top of RAM is defined to be the TSEG base address. |
| 98 | */ |
| 99 | *size = CONFIG_SMM_RESERVED_SIZE; |
| 100 | *base = (void *)(northbridge_get_tseg_base() |
| 101 | + CONFIG_SMM_RESERVED_SIZE); |
| 102 | } |
| 103 | |
Arthur Heymans | 2dcc3a5 | 2018-06-03 10:39:16 +0200 | [diff] [blame] | 104 | /* platform_enter_postcar() determines the stack to use after |
| 105 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 106 | * and continues execution in postcar stage. */ |
| 107 | void platform_enter_postcar(void) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 108 | { |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 109 | struct postcar_frame pcf; |
| 110 | uintptr_t top_of_ram; |
| 111 | |
Kyösti Mälkki | 6e2d0c1 | 2019-06-28 10:08:51 +0300 | [diff] [blame] | 112 | if (postcar_frame_init(&pcf, 0)) |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 113 | die("Unable to initialize postcar frame.\n"); |
| 114 | |
| 115 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 089b908 | 2018-05-27 14:37:32 +0200 | [diff] [blame] | 116 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 117 | |
| 118 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 119 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 120 | |
Arthur Heymans | cf3076e | 2018-04-10 12:57:42 +0200 | [diff] [blame] | 121 | /* Cache 8 MiB region below the top of ram and 2 MiB above top of |
| 122 | * ram to cover both cbmem as the TSEG region. |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 123 | */ |
| 124 | top_of_ram = (uintptr_t)cbmem_top(); |
Arthur Heymans | cf3076e | 2018-04-10 12:57:42 +0200 | [diff] [blame] | 125 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, |
| 126 | MTRR_TYPE_WRBACK); |
| 127 | postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), |
| 128 | northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); |
Kyösti Mälkki | 823020d | 2016-07-22 22:53:19 +0300 | [diff] [blame] | 129 | |
Arthur Heymans | 2dcc3a5 | 2018-06-03 10:39:16 +0200 | [diff] [blame] | 130 | run_postcar_phase(&pcf); |
| 131 | |
| 132 | /* We do not return here. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 133 | } |