Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
| 7 | #include <device/pci_ops.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 9 | #include <delay.h> |
Vladimir Serbinenko | 75c8387 | 2014-09-05 01:01:31 +0200 | [diff] [blame] | 10 | #include <device/azalia_device.h> |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 11 | #include "pch.h" |
| 12 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 13 | static int codec_detect(u8 *base) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 14 | { |
| 15 | u8 reg8; |
| 16 | |
Angel Pons | 7f839f6 | 2020-12-05 19:02:14 +0100 | [diff] [blame] | 17 | if (azalia_exit_reset(base) < 0) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 18 | goto no_codec; |
| 19 | |
| 20 | /* Write back the value once reset bit is set. */ |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 21 | write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 22 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 23 | /* Read in Codec location (BAR + 0xe)[2..0] */ |
Elyes HAOUAS | 59236d5 | 2020-08-03 15:36:52 +0200 | [diff] [blame] | 24 | reg8 = read8(base + HDA_STATESTS_REG); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 25 | reg8 &= 0x0f; |
| 26 | if (!reg8) |
| 27 | goto no_codec; |
| 28 | |
| 29 | return reg8; |
| 30 | |
| 31 | no_codec: |
Angel Pons | 2e0053b | 2020-12-05 19:06:55 +0100 | [diff] [blame] | 32 | /* Codec not found, put HDA back in reset */ |
| 33 | azalia_enter_reset(base); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 34 | printk(BIOS_DEBUG, "Azalia: No codec!\n"); |
| 35 | return 0; |
| 36 | } |
| 37 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 38 | static void azalia_init(struct device *dev) |
| 39 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 40 | u8 *base; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 41 | struct resource *res; |
| 42 | u32 codec_mask; |
| 43 | u8 reg8; |
| 44 | u16 reg16; |
| 45 | u32 reg32; |
| 46 | |
| 47 | /* Find base address */ |
Angel Pons | f32ae10 | 2021-11-03 13:07:14 +0100 | [diff] [blame] | 48 | res = probe_resource(dev, PCI_BASE_ADDRESS_0); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 49 | if (!res) |
| 50 | return; |
| 51 | |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 52 | // NOTE this will break as soon as the Azalia gets a bar above 4G. |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 53 | // Is there anything we can do about it? |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 54 | base = res2mmio(res, 0, 0); |
Patrick Rudolph | 819c206 | 2019-11-29 19:27:37 +0100 | [diff] [blame] | 55 | printk(BIOS_DEBUG, "Azalia: base = %p\n", base); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 56 | |
| 57 | if (RCBA32(0x2030) & (1 << 31)) { |
| 58 | reg32 = pci_read_config32(dev, 0x120); |
| 59 | reg32 &= 0xf8ffff01; |
| 60 | reg32 |= (1 << 24); // 2 << 24 for server |
| 61 | reg32 |= RCBA32(0x2030) & 0xfe; |
| 62 | pci_write_config32(dev, 0x120, reg32); |
| 63 | |
| 64 | reg16 = pci_read_config16(dev, 0x78); |
| 65 | reg16 |= (1 << 11); |
| 66 | pci_write_config16(dev, 0x78, reg16); |
| 67 | } else |
| 68 | printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); |
| 69 | |
| 70 | reg32 = pci_read_config32(dev, 0x114); |
| 71 | reg32 &= ~0xfe; |
| 72 | pci_write_config32(dev, 0x114, reg32); |
| 73 | |
| 74 | // Set VCi enable bit |
| 75 | reg32 = pci_read_config32(dev, 0x120); |
| 76 | reg32 |= (1 << 31); |
| 77 | pci_write_config32(dev, 0x120, reg32); |
| 78 | |
| 79 | // Enable HDMI codec: |
| 80 | reg32 = pci_read_config32(dev, 0xc4); |
| 81 | reg32 |= (1 << 1); |
| 82 | pci_write_config32(dev, 0xc4, reg32); |
| 83 | |
| 84 | reg8 = pci_read_config8(dev, 0x43); |
| 85 | reg8 |= (1 << 6); |
| 86 | pci_write_config8(dev, 0x43, reg8); |
| 87 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 88 | reg32 = pci_read_config32(dev, 0xd0); |
| 89 | reg32 &= ~(1 << 31); |
| 90 | pci_write_config32(dev, 0xd0, reg32); |
| 91 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 92 | /* Set Bus Master */ |
Elyes HAOUAS | 8b6dfde | 2020-04-28 09:58:21 +0200 | [diff] [blame] | 93 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 94 | |
| 95 | pci_write_config8(dev, 0x3c, 0x0a); // unused? |
| 96 | |
| 97 | /* Codec Initialization Programming Sequence */ |
| 98 | |
| 99 | /* Take controller out of reset */ |
Elyes HAOUAS | 59236d5 | 2020-08-03 15:36:52 +0200 | [diff] [blame] | 100 | reg32 = read32(base + HDA_GCTL_REG); |
| 101 | reg32 |= HDA_GCTL_CRST; |
| 102 | write32(base + HDA_GCTL_REG, reg32); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 103 | /* Wait 1ms */ |
| 104 | udelay(1000); |
| 105 | |
| 106 | // |
| 107 | reg8 = pci_read_config8(dev, 0x40); // Audio Control |
| 108 | reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb |
| 109 | pci_write_config8(dev, 0x40, reg8); |
| 110 | |
| 111 | reg8 = pci_read_config8(dev, 0x4d); // Docking Status |
| 112 | reg8 &= ~(1 << 7); // Docking not supported |
| 113 | pci_write_config8(dev, 0x4d, reg8); |
| 114 | |
| 115 | codec_mask = codec_detect(base); |
| 116 | |
| 117 | if (codec_mask) { |
| 118 | printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); |
Angel Pons | aae6b55 | 2021-11-10 18:10:38 +0100 | [diff] [blame^] | 119 | azalia_codecs_init(base, codec_mask); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | /* Enable dynamic clock gating */ |
| 123 | reg8 = pci_read_config8(dev, 0x43); |
| 124 | reg8 &= ~0x7; |
| 125 | reg8 |= (1 << 2) | (1 << 0); |
| 126 | pci_write_config8(dev, 0x43, reg8); |
| 127 | } |
| 128 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 129 | static struct device_operations azalia_ops = { |
| 130 | .read_resources = pci_dev_read_resources, |
| 131 | .set_resources = pci_dev_set_resources, |
| 132 | .enable_resources = pci_dev_enable_resources, |
| 133 | .init = azalia_init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 134 | .ops_pci = &pci_dev_ops_pci, |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 135 | }; |
| 136 | |
Felix Singer | 838fbc7 | 2019-11-21 21:23:32 +0100 | [diff] [blame] | 137 | static const unsigned short pci_device_ids[] = { |
| 138 | 0x1c20, |
| 139 | 0x1e20, |
| 140 | PCI_DID_INTEL_IBEXPEAK_AUDIO, |
| 141 | 0 |
| 142 | }; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 143 | |
| 144 | static const struct pci_driver pch_azalia __pci_driver = { |
| 145 | .ops = &azalia_ops, |
| 146 | .vendor = PCI_VENDOR_ID_INTEL, |
| 147 | .devices = pci_device_ids, |
| 148 | }; |