Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
| 7 | #include <device/pci_ops.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 9 | #include <delay.h> |
Vladimir Serbinenko | 75c8387 | 2014-09-05 01:01:31 +0200 | [diff] [blame] | 10 | #include <device/azalia_device.h> |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 11 | #include "pch.h" |
| 12 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 13 | static int set_bits(void *port, u32 mask, u32 val) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 14 | { |
| 15 | u32 reg32; |
| 16 | int count; |
| 17 | |
| 18 | /* Write (val & mask) to port */ |
| 19 | val &= mask; |
| 20 | reg32 = read32(port); |
| 21 | reg32 &= ~mask; |
| 22 | reg32 |= val; |
| 23 | write32(port, reg32); |
| 24 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 25 | /* Wait for readback of register to match what was just written to it */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 26 | count = 50; |
| 27 | do { |
| 28 | /* Wait 1ms based on BKDG wait time */ |
| 29 | mdelay(1); |
| 30 | reg32 = read32(port); |
| 31 | reg32 &= mask; |
| 32 | } while ((reg32 != val) && --count); |
| 33 | |
| 34 | /* Timeout occurred */ |
| 35 | if (!count) |
| 36 | return -1; |
| 37 | return 0; |
| 38 | } |
| 39 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 40 | static int codec_detect(u8 *base) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 41 | { |
| 42 | u8 reg8; |
| 43 | |
| 44 | /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 45 | if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) == -1) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 46 | goto no_codec; |
| 47 | |
| 48 | /* Write back the value once reset bit is set. */ |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 49 | write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 50 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 51 | /* Read in Codec location (BAR + 0xe)[2..0] */ |
Elyes HAOUAS | 59236d5 | 2020-08-03 15:36:52 +0200 | [diff] [blame] | 52 | reg8 = read8(base + HDA_STATESTS_REG); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 53 | reg8 &= 0x0f; |
| 54 | if (!reg8) |
| 55 | goto no_codec; |
| 56 | |
| 57 | return reg8; |
| 58 | |
| 59 | no_codec: |
| 60 | /* Codec Not found */ |
| 61 | /* Put HDA back in reset (BAR + 0x8) [0] */ |
Elyes HAOUAS | 59236d5 | 2020-08-03 15:36:52 +0200 | [diff] [blame] | 62 | set_bits(base + HDA_GCTL_REG, 1, 0); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 63 | printk(BIOS_DEBUG, "Azalia: No codec!\n"); |
| 64 | return 0; |
| 65 | } |
| 66 | |
Elyes HAOUAS | e414a4e | 2019-01-03 10:40:43 +0100 | [diff] [blame] | 67 | static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 68 | { |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 69 | int idx = 0; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 70 | |
| 71 | while (idx < (cim_verb_data_size / sizeof(u32))) { |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 72 | u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 73 | if (cim_verb_data[idx] != viddid) { |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 74 | idx += verb_size + 3; // skip verb + header |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 75 | continue; |
| 76 | } |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 77 | *verb = &cim_verb_data[idx + 3]; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 78 | return verb_size; |
| 79 | } |
| 80 | |
| 81 | /* Not all codecs need to load another verb */ |
| 82 | return 0; |
| 83 | } |
| 84 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 85 | /* |
| 86 | * Wait 50usec for the codec to indicate it is ready. |
| 87 | * No response would imply that the codec is non-operative. |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 88 | */ |
| 89 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 90 | static int wait_for_ready(u8 *base) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 91 | { |
| 92 | /* Use a 1msec timeout */ |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 93 | int timeout = 1000; |
| 94 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 95 | while (timeout--) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 96 | u32 reg32 = read32(base + HDA_ICII_REG); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 97 | if (!(reg32 & HDA_ICII_BUSY)) |
| 98 | return 0; |
| 99 | udelay(1); |
| 100 | } |
| 101 | |
| 102 | return -1; |
| 103 | } |
| 104 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 105 | /* |
| 106 | * Wait 50usec for the codec to indicate that it accepted the previous command. |
| 107 | * No response would imply that the code is non-operative. |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 108 | */ |
| 109 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 110 | static int wait_for_valid(u8 *base) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 111 | { |
| 112 | u32 reg32; |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 113 | /* Use a 1msec timeout */ |
| 114 | int timeout = 1000; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 115 | |
| 116 | /* Send the verb to the codec */ |
| 117 | reg32 = read32(base + HDA_ICII_REG); |
| 118 | reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; |
| 119 | write32(base + HDA_ICII_REG, reg32); |
| 120 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 121 | while (timeout--) { |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 122 | reg32 = read32(base + HDA_ICII_REG); |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 123 | if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 124 | return 0; |
| 125 | udelay(1); |
| 126 | } |
| 127 | |
| 128 | return -1; |
| 129 | } |
| 130 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 131 | static void codec_init(struct device *dev, u8 *base, int addr) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 132 | { |
| 133 | u32 reg32; |
| 134 | const u32 *verb; |
| 135 | u32 verb_size; |
| 136 | int i; |
| 137 | |
| 138 | printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); |
| 139 | |
| 140 | /* 1 */ |
| 141 | if (wait_for_ready(base) == -1) { |
| 142 | printk(BIOS_DEBUG, " codec not ready.\n"); |
| 143 | return; |
| 144 | } |
| 145 | |
| 146 | reg32 = (addr << 28) | 0x000f0000; |
Elyes HAOUAS | 59236d5 | 2020-08-03 15:36:52 +0200 | [diff] [blame] | 147 | write32(base + HDA_IC_REG, reg32); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 148 | |
| 149 | if (wait_for_valid(base) == -1) { |
| 150 | printk(BIOS_DEBUG, " codec not valid.\n"); |
| 151 | return; |
| 152 | } |
| 153 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 154 | /* 2 */ |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 155 | reg32 = read32(base + HDA_IR_REG); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 156 | printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); |
| 157 | verb_size = find_verb(dev, reg32, &verb); |
| 158 | |
| 159 | if (!verb_size) { |
| 160 | printk(BIOS_DEBUG, "Azalia: No verb!\n"); |
| 161 | return; |
| 162 | } |
| 163 | printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); |
| 164 | |
| 165 | /* 3 */ |
| 166 | for (i = 0; i < verb_size; i++) { |
| 167 | if (wait_for_ready(base) == -1) |
| 168 | return; |
| 169 | |
Elyes HAOUAS | 59236d5 | 2020-08-03 15:36:52 +0200 | [diff] [blame] | 170 | write32(base + HDA_IC_REG, verb[i]); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 171 | |
| 172 | if (wait_for_valid(base) == -1) |
| 173 | return; |
| 174 | } |
| 175 | printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); |
| 176 | } |
| 177 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 178 | static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 179 | { |
| 180 | int i; |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 181 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 182 | for (i = 3; i >= 0; i--) { |
| 183 | if (codec_mask & (1 << i)) |
| 184 | codec_init(dev, base, i); |
| 185 | } |
| 186 | |
| 187 | for (i = 0; i < pc_beep_verbs_size; i++) { |
| 188 | if (wait_for_ready(base) == -1) |
| 189 | return; |
| 190 | |
Elyes HAOUAS | 59236d5 | 2020-08-03 15:36:52 +0200 | [diff] [blame] | 191 | write32(base + HDA_IC_REG, pc_beep_verbs[i]); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 192 | |
| 193 | if (wait_for_valid(base) == -1) |
| 194 | return; |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | static void azalia_init(struct device *dev) |
| 199 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 200 | u8 *base; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 201 | struct resource *res; |
| 202 | u32 codec_mask; |
| 203 | u8 reg8; |
| 204 | u16 reg16; |
| 205 | u32 reg32; |
| 206 | |
| 207 | /* Find base address */ |
| 208 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 209 | if (!res) |
| 210 | return; |
| 211 | |
Elyes HAOUAS | 6ea24ff | 2020-08-11 09:21:24 +0200 | [diff] [blame] | 212 | // NOTE this will break as soon as the Azalia get's a bar above 4G. |
| 213 | // Is there anything we can do about it? |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 214 | base = res2mmio(res, 0, 0); |
Patrick Rudolph | 819c206 | 2019-11-29 19:27:37 +0100 | [diff] [blame^] | 215 | printk(BIOS_DEBUG, "Azalia: base = %p\n", base); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 216 | |
| 217 | if (RCBA32(0x2030) & (1 << 31)) { |
| 218 | reg32 = pci_read_config32(dev, 0x120); |
| 219 | reg32 &= 0xf8ffff01; |
| 220 | reg32 |= (1 << 24); // 2 << 24 for server |
| 221 | reg32 |= RCBA32(0x2030) & 0xfe; |
| 222 | pci_write_config32(dev, 0x120, reg32); |
| 223 | |
| 224 | reg16 = pci_read_config16(dev, 0x78); |
| 225 | reg16 |= (1 << 11); |
| 226 | pci_write_config16(dev, 0x78, reg16); |
| 227 | } else |
| 228 | printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); |
| 229 | |
| 230 | reg32 = pci_read_config32(dev, 0x114); |
| 231 | reg32 &= ~0xfe; |
| 232 | pci_write_config32(dev, 0x114, reg32); |
| 233 | |
| 234 | // Set VCi enable bit |
| 235 | reg32 = pci_read_config32(dev, 0x120); |
| 236 | reg32 |= (1 << 31); |
| 237 | pci_write_config32(dev, 0x120, reg32); |
| 238 | |
| 239 | // Enable HDMI codec: |
| 240 | reg32 = pci_read_config32(dev, 0xc4); |
| 241 | reg32 |= (1 << 1); |
| 242 | pci_write_config32(dev, 0xc4, reg32); |
| 243 | |
| 244 | reg8 = pci_read_config8(dev, 0x43); |
| 245 | reg8 |= (1 << 6); |
| 246 | pci_write_config8(dev, 0x43, reg8); |
| 247 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 248 | reg32 = pci_read_config32(dev, 0xd0); |
| 249 | reg32 &= ~(1 << 31); |
| 250 | pci_write_config32(dev, 0xd0, reg32); |
| 251 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 252 | /* Set Bus Master */ |
Elyes HAOUAS | 8b6dfde | 2020-04-28 09:58:21 +0200 | [diff] [blame] | 253 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 254 | |
| 255 | pci_write_config8(dev, 0x3c, 0x0a); // unused? |
| 256 | |
| 257 | /* Codec Initialization Programming Sequence */ |
| 258 | |
| 259 | /* Take controller out of reset */ |
Elyes HAOUAS | 59236d5 | 2020-08-03 15:36:52 +0200 | [diff] [blame] | 260 | reg32 = read32(base + HDA_GCTL_REG); |
| 261 | reg32 |= HDA_GCTL_CRST; |
| 262 | write32(base + HDA_GCTL_REG, reg32); |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 263 | /* Wait 1ms */ |
| 264 | udelay(1000); |
| 265 | |
| 266 | // |
| 267 | reg8 = pci_read_config8(dev, 0x40); // Audio Control |
| 268 | reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb |
| 269 | pci_write_config8(dev, 0x40, reg8); |
| 270 | |
| 271 | reg8 = pci_read_config8(dev, 0x4d); // Docking Status |
| 272 | reg8 &= ~(1 << 7); // Docking not supported |
| 273 | pci_write_config8(dev, 0x4d, reg8); |
| 274 | |
| 275 | codec_mask = codec_detect(base); |
| 276 | |
| 277 | if (codec_mask) { |
| 278 | printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); |
| 279 | codecs_init(dev, base, codec_mask); |
| 280 | } |
| 281 | |
| 282 | /* Enable dynamic clock gating */ |
| 283 | reg8 = pci_read_config8(dev, 0x43); |
| 284 | reg8 &= ~0x7; |
| 285 | reg8 |= (1 << 2) | (1 << 0); |
| 286 | pci_write_config8(dev, 0x43, reg8); |
| 287 | } |
| 288 | |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 289 | static struct device_operations azalia_ops = { |
| 290 | .read_resources = pci_dev_read_resources, |
| 291 | .set_resources = pci_dev_set_resources, |
| 292 | .enable_resources = pci_dev_enable_resources, |
| 293 | .init = azalia_init, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 294 | .ops_pci = &pci_dev_ops_pci, |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 295 | }; |
| 296 | |
Felix Singer | 838fbc7 | 2019-11-21 21:23:32 +0100 | [diff] [blame] | 297 | static const unsigned short pci_device_ids[] = { |
| 298 | 0x1c20, |
| 299 | 0x1e20, |
| 300 | PCI_DID_INTEL_IBEXPEAK_AUDIO, |
| 301 | 0 |
| 302 | }; |
Vladimir Serbinenko | 888d559 | 2013-11-13 17:53:38 +0100 | [diff] [blame] | 303 | |
| 304 | static const struct pci_driver pch_azalia __pci_driver = { |
| 305 | .ops = &azalia_ops, |
| 306 | .vendor = PCI_VENDOR_ID_INTEL, |
| 307 | .devices = pci_device_ids, |
| 308 | }; |