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Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010015 */
16
Elyes HAOUAS6d19a202018-11-22 11:15:29 +010017#include <arch/acpi.h>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010018DefinitionBlock(
19 "dsdt.aml",
20 "DSDT",
Elyes HAOUAS0cca6e22018-11-13 14:23:29 +010021 0x02, /* DSDT revision: ACPI v2.0 and up */
Elyes HAOUAS6d19a202018-11-22 11:15:29 +010022 OEM_ID,
23 ACPI_TABLE_CREATOR,
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010024 0x20140108 /* OEM revision */
25)
26{
27 /* Some generic macros */
28 #include "acpi/platform.asl"
29
30 /* global NVS and variables */
31 #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
32
33 /* General Purpose Events */
34 #include "acpi/gpe.asl"
35
Arthur Heymansaaced4a2018-11-28 13:53:15 +010036 #include <cpu/intel/common/acpi/cpu.asl>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010037
38 Scope (\_SB) {
39 Device (PCI0)
40 {
41 #include <northbridge/intel/nehalem/acpi/nehalem.asl>
42 #include <southbridge/intel/bd82x6x/acpi/pch.asl>
Nico Huber954a55b2015-08-27 13:31:46 +020043
44 #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010045 }
46 Device (UNCR)
47 {
48 Name (_BBN, 0xFF)
49 Name (_ADR, 0x00)
50 Name (RID, 0x00)
51 Name (_HID, EisaId ("PNP0A03"))
52 Name (_CRS, ResourceTemplate ()
53 {
54 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
55 0x0000, /* Granularity */
56 0x00FF, /* Range Minimum */
57 0x00FF, /* Range Maximum */
58 0x0000, /* Translation Offset */
59 0x0001, /* Length */
60 ,, )
61 })
62 Device (SAD)
63 {
64 Name (_ADR, 0x01)
65 Name (RID, 0x00)
66 OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
67 Field (SADC, DWordAcc, NoLock, Preserve)
68 {
69 Offset (0x40),
70 PAM0, 8,
71 PAM1, 8,
72 PAM2, 8,
73 PAM3, 8,
74 PAM4, 8,
75 PAM5, 8,
76 PAM6, 8
77 }
78 }
79 }
80 }
81
Vladimir Serbinenkob1ccccc2014-02-19 22:20:14 +010082 /* Chipset specific sleep states */
83 #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
84}