Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | d06f800 | 2021-01-27 20:25:51 +0200 | [diff] [blame] | 4 | #include <acpi/acpigen.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | #include <cbmem.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | #include <cpu/x86/smm.h> |
| 7 | #include <device/device.h> |
| 8 | #include <device/pci.h> |
| 9 | #include <device/pci_ids.h> |
Elyes HAOUAS | 32da343 | 2020-05-17 17:15:31 +0200 | [diff] [blame] | 10 | #include <cpu/x86/lapic_def.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 11 | #include <fsp/util.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 12 | #include <soc/iomap.h> |
| 13 | #include <soc/iosf.h> |
| 14 | #include <soc/pci_devs.h> |
| 15 | #include <soc/ramstage.h> |
Harry Pan | 43dcbfd | 2016-08-11 14:35:04 +0800 | [diff] [blame] | 16 | #include <stddef.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 17 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 18 | /* |
| 19 | * Host Memory Map: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | * |
| 21 | * +--------------------------+ BMBOUND_HI |
| 22 | * | Usable DRAM | |
| 23 | * +--------------------------+ 4GiB |
| 24 | * | PCI Address Space | |
| 25 | * +--------------------------+ BMBOUND |
| 26 | * | TPM | |
| 27 | * +--------------------------+ IMR2 |
| 28 | * | TXE | |
| 29 | * +--------------------------+ IMR1 |
| 30 | * | iGD | |
| 31 | * +--------------------------+ |
| 32 | * | GTT | |
| 33 | * +--------------------------+ SMMRRH, IRM0 |
| 34 | * | TSEG | |
| 35 | * +--------------------------+ SMMRRL |
| 36 | * | Usable DRAM | |
| 37 | * +--------------------------+ 0 |
| 38 | * |
| 39 | * Note that there are really only a few regions that need to enumerated w.r.t. |
Frans Hendriks | b81dcc6 | 2018-12-10 10:30:37 +0100 | [diff] [blame] | 40 | * coreboot's resource model: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 41 | * |
| 42 | * +--------------------------+ BMBOUND_HI |
| 43 | * | Cacheable/Usable | |
| 44 | * +--------------------------+ 4GiB |
| 45 | * |
| 46 | * +--------------------------+ BMBOUND |
| 47 | * | Uncacheable/Reserved | |
| 48 | * +--------------------------+ SMMRRH |
| 49 | * | Cacheable/Reserved | |
| 50 | * +--------------------------+ SMMRRL |
| 51 | * | Cacheable/Usable | |
| 52 | * +--------------------------+ 0 |
| 53 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 54 | uint32_t nc_read_top_of_low_memory(void) |
| 55 | { |
Kyösti Mälkki | fcbbb91 | 2020-04-20 10:21:39 +0300 | [diff] [blame] | 56 | static uint32_t tolm; |
Harry Pan | 43dcbfd | 2016-08-11 14:35:04 +0800 | [diff] [blame] | 57 | |
| 58 | if (tolm) |
| 59 | return tolm; |
| 60 | |
| 61 | tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); |
| 62 | |
| 63 | return tolm; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 64 | } |
| 65 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 66 | static void nc_read_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 67 | { |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 68 | uint64_t mmconf; |
| 69 | uint64_t bmbound; |
| 70 | uint64_t bmbound_hi; |
Kyösti Mälkki | 14222d8 | 2019-08-05 15:10:18 +0300 | [diff] [blame] | 71 | uintptr_t smm_base; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 72 | size_t smm_size; |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 73 | uint64_t tseg_base; |
| 74 | uint64_t tseg_top; |
| 75 | uint64_t fsp_res_base; |
Frans Hendriks | c6d672f | 2018-10-30 15:07:39 +0100 | [diff] [blame] | 76 | void *fsp_reserved_memory_area; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 77 | int index = 0; |
| 78 | |
| 79 | /* Read standard PCI resources. */ |
| 80 | pci_dev_read_resources(dev); |
| 81 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 82 | /* Determine TSEG data */ |
| 83 | smm_region(&smm_base, &smm_size); |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 84 | tseg_base = smm_base; |
| 85 | tseg_top = tseg_base + smm_size; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 86 | |
| 87 | /* Determine the base of the FSP reserved memory */ |
Frans Hendriks | c6d672f | 2018-10-30 15:07:39 +0100 | [diff] [blame] | 88 | fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); |
| 89 | if (fsp_reserved_memory_area) { |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 90 | fsp_res_base = (uintptr_t)fsp_reserved_memory_area; |
Frans Hendriks | c6d672f | 2018-10-30 15:07:39 +0100 | [diff] [blame] | 91 | } else { |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 92 | /* If no FSP reserved area */ |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 93 | fsp_res_base = tseg_base; |
Frans Hendriks | c6d672f | 2018-10-30 15:07:39 +0100 | [diff] [blame] | 94 | } |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 95 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 96 | /* PCIe memory-mapped config space access - 256 MiB. */ |
| 97 | mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); |
Kyösti Mälkki | 5a55a45 | 2021-06-24 20:49:05 +0300 | [diff] [blame] | 98 | mmio_range(dev, BUNIT_MMCONF_REG, mmconf, CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 99 | |
| 100 | /* 0 -> 0xa0000 */ |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 101 | ram_from_to(dev, index++, 0, 0xa0000); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 102 | |
Frans Hendriks | c6d672f | 2018-10-30 15:07:39 +0100 | [diff] [blame] | 103 | /* High memory -> fsp_res_base - cacheable and usable */ |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 104 | ram_from_to(dev, index++, 1 * MiB, fsp_res_base); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 105 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 106 | /* fsp_res_base -> tseg_top - Reserved */ |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 107 | reserved_ram_from_to(dev, index++, fsp_res_base, tseg_top); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 108 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 109 | /* TSEG TOP -> bmbound is memory backed mmio. */ |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 110 | bmbound = nc_read_top_of_low_memory(); |
| 111 | mmio_from_to(dev, index++, tseg_top, bmbound); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 112 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 113 | /* |
| 114 | * The BMBOUND_HI register matches register bits of 31:24 with address |
| 115 | * bits of 35:28. Therefore, shift register to align properly. |
| 116 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 117 | bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 118 | bmbound_hi <<= 4; |
Kyösti Mälkki | 0a18d64 | 2021-06-28 21:43:31 +0300 | [diff] [blame] | 119 | upper_ram_end(dev, index++, bmbound_hi); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 120 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 121 | /* |
| 122 | * Reserve everything between A segment and 1MB: |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 123 | * |
| 124 | * 0xa0000 - 0xbffff: legacy VGA |
| 125 | * 0xc0000 - 0xfffff: RAM |
| 126 | */ |
Arthur Heymans | 43169fe | 2023-07-05 11:49:59 +0200 | [diff] [blame] | 127 | mmio_from_to(dev, index++, 0xa0000, 0xc0000); |
| 128 | reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 129 | |
Frans Hendriks | d97eb64 | 2018-11-26 11:01:56 +0100 | [diff] [blame] | 130 | /* |
| 131 | * Reserve local APIC |
| 132 | */ |
Kyösti Mälkki | 5c3cbcd | 2021-06-25 13:02:55 +0300 | [diff] [blame] | 133 | mmio_range(dev, index++, LAPIC_DEFAULT_BASE, 1 * MiB); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 134 | } |
| 135 | |
Kyösti Mälkki | d06f800 | 2021-01-27 20:25:51 +0200 | [diff] [blame] | 136 | static void nc_generate_ssdt(const struct device *dev) |
| 137 | { |
| 138 | generate_cpu_entries(dev); |
| 139 | |
| 140 | acpigen_write_scope("\\"); |
| 141 | acpigen_write_name_dword("TOLM", nc_read_top_of_low_memory()); |
| 142 | acpigen_pop_len(); |
| 143 | } |
| 144 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 145 | static struct device_operations nc_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 146 | .read_resources = nc_read_resources, |
Kyösti Mälkki | d06f800 | 2021-01-27 20:25:51 +0200 | [diff] [blame] | 147 | .acpi_fill_ssdt = nc_generate_ssdt, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 148 | .ops_pci = &soc_pci_ops, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 149 | }; |
| 150 | |
| 151 | static const struct pci_driver nc_driver __pci_driver = { |
| 152 | .ops = &nc_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 153 | .vendor = PCI_VID_INTEL, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 154 | .device = SOC_DEVID, |
| 155 | }; |