Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 16 | #include <arch/cpu.h> |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame^] | 17 | #include <arch/romstage.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 18 | #include <arch/symbols.h> |
| 19 | #include <assert.h> |
| 20 | #include <cpu/x86/mtrr.h> |
Naresh G Solanki | 79239b7 | 2016-11-16 21:34:41 +0530 | [diff] [blame] | 21 | #include <cpu/x86/msr.h> |
Kyösti Mälkki | b2a5f0b | 2019-08-04 19:54:32 +0300 | [diff] [blame] | 22 | #include <cpu/x86/smm.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 23 | #include <cbmem.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 24 | #include <console/console.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 25 | #include <device/pci_def.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 26 | #include <fsp/util.h> |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 27 | #include <intelblocks/pmclib.h> |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 28 | #include <memory_info.h> |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 29 | #include <smbios.h> |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 30 | #include <soc/intel/common/smbios.h> |
Naresh G Solanki | 79239b7 | 2016-11-16 21:34:41 +0530 | [diff] [blame] | 31 | #include <soc/msr.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 32 | #include <soc/pci_devs.h> |
| 33 | #include <soc/pm.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 34 | #include <soc/romstage.h> |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 35 | #include <string.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 36 | #include <timestamp.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 37 | #include <security/vboot/vboot_common.h> |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 38 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 39 | #include "../chip.h" |
| 40 | |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 41 | #define FSP_SMBIOS_MEMORY_INFO_GUID \ |
| 42 | { \ |
| 43 | 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ |
| 44 | 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ |
| 45 | } |
| 46 | |
Subrata Banik | 54fa28e | 2018-02-07 14:59:34 +0530 | [diff] [blame] | 47 | /* Memory Channel Present Status */ |
| 48 | enum { |
| 49 | CHANNEL_NOT_PRESENT, |
| 50 | CHANNEL_DISABLED, |
| 51 | CHANNEL_PRESENT |
| 52 | }; |
| 53 | |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 54 | /* Save the DIMM information for SMBIOS table 17 */ |
| 55 | static void save_dimm_info(void) |
| 56 | { |
| 57 | int channel, dimm, dimm_max, index; |
| 58 | size_t hob_size; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 59 | uint8_t ddr_type; |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 60 | const CONTROLLER_INFO *ctrlr_info; |
| 61 | const CHANNEL_INFO *channel_info; |
| 62 | const DIMM_INFO *src_dimm; |
| 63 | struct dimm_info *dest_dimm; |
| 64 | struct memory_info *mem_info; |
| 65 | const MEMORY_INFO_DATA_HOB *memory_info_hob; |
Subrata Banik | 54fa28e | 2018-02-07 14:59:34 +0530 | [diff] [blame] | 66 | const uint8_t smbios_memory_info_guid[16] = |
| 67 | FSP_SMBIOS_MEMORY_INFO_GUID; |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 68 | |
| 69 | /* Locate the memory info HOB, presence validated by raminit */ |
| 70 | memory_info_hob = |
| 71 | fsp_find_extension_hob_by_guid(smbios_memory_info_guid, |
| 72 | &hob_size); |
Subrata Banik | 54fa28e | 2018-02-07 14:59:34 +0530 | [diff] [blame] | 73 | if (memory_info_hob == NULL || hob_size == 0) { |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 74 | printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); |
| 75 | return; |
| 76 | } |
| 77 | |
| 78 | /* |
| 79 | * Allocate CBMEM area for DIMM information used to populate SMBIOS |
| 80 | * table 17 |
| 81 | */ |
| 82 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 83 | if (mem_info == NULL) { |
| 84 | printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); |
| 85 | return; |
| 86 | } |
| 87 | memset(mem_info, 0, sizeof(*mem_info)); |
| 88 | |
| 89 | /* Describe the first N DIMMs in the system */ |
| 90 | index = 0; |
| 91 | dimm_max = ARRAY_SIZE(mem_info->dimm); |
| 92 | ctrlr_info = &memory_info_hob->Controller[0]; |
Nico Huber | 9dc62ea | 2017-07-19 15:45:14 +0200 | [diff] [blame] | 93 | for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { |
Balaji Manigandan B | bd55c02 | 2017-09-22 14:27:56 +0530 | [diff] [blame] | 94 | channel_info = &ctrlr_info->ChannelInfo[channel]; |
Subrata Banik | 54fa28e | 2018-02-07 14:59:34 +0530 | [diff] [blame] | 95 | if (channel_info->Status != CHANNEL_PRESENT) |
Nico Huber | 9dc62ea | 2017-07-19 15:45:14 +0200 | [diff] [blame] | 96 | continue; |
| 97 | for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { |
Balaji Manigandan B | bd55c02 | 2017-09-22 14:27:56 +0530 | [diff] [blame] | 98 | src_dimm = &channel_info->DimmInfo[dimm]; |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 99 | dest_dimm = &mem_info->dimm[index]; |
| 100 | |
Nico Huber | 9dc62ea | 2017-07-19 15:45:14 +0200 | [diff] [blame] | 101 | if (src_dimm->Status != DIMM_PRESENT) |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 102 | continue; |
| 103 | |
Elyes HAOUAS | 0ce41f1 | 2018-11-13 10:03:31 +0100 | [diff] [blame] | 104 | switch (memory_info_hob->MemoryType) { |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 105 | case MRC_DDR_TYPE_DDR4: |
Elyes HAOUAS | 28114ae | 2018-11-14 17:51:00 +0100 | [diff] [blame] | 106 | ddr_type = MEMORY_TYPE_DDR4; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 107 | break; |
| 108 | case MRC_DDR_TYPE_DDR3: |
Elyes HAOUAS | 28114ae | 2018-11-14 17:51:00 +0100 | [diff] [blame] | 109 | ddr_type = MEMORY_TYPE_DDR3; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 110 | break; |
| 111 | case MRC_DDR_TYPE_LPDDR3: |
Elyes HAOUAS | 28114ae | 2018-11-14 17:51:00 +0100 | [diff] [blame] | 112 | ddr_type = MEMORY_TYPE_LPDDR3; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 113 | break; |
| 114 | default: |
Elyes HAOUAS | 28114ae | 2018-11-14 17:51:00 +0100 | [diff] [blame] | 115 | ddr_type = MEMORY_TYPE_UNKNOWN; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 116 | break; |
| 117 | } |
Christian Walter | f972322 | 2019-05-28 10:37:24 +0200 | [diff] [blame] | 118 | u8 memProfNum = memory_info_hob->MemoryProfile; |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 119 | |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 120 | /* Populate the DIMM information */ |
| 121 | dimm_info_fill(dest_dimm, |
| 122 | src_dimm->DimmCapacity, |
Barnali Sarkar | f7f01f7 | 2018-01-11 16:40:54 +0530 | [diff] [blame] | 123 | ddr_type, |
Balaji Manigandan B | bd55c02 | 2017-09-22 14:27:56 +0530 | [diff] [blame] | 124 | memory_info_hob->ConfiguredMemoryClockSpeed, |
Francois Toguo | 993f68a | 2019-02-04 17:05:51 -0800 | [diff] [blame] | 125 | src_dimm->RankInDimm, |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 126 | channel_info->ChannelId, |
| 127 | src_dimm->DimmId, |
| 128 | (const char *)src_dimm->ModulePartNum, |
| 129 | sizeof(src_dimm->ModulePartNum), |
Duncan Laurie | 46340d0 | 2019-05-17 14:57:31 -0600 | [diff] [blame] | 130 | src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, |
Christian Walter | f972322 | 2019-05-28 10:37:24 +0200 | [diff] [blame] | 131 | memory_info_hob->DataWidth, |
| 132 | memory_info_hob->VddVoltage[memProfNum], |
Duncan Laurie | 1a86cda | 2019-06-10 14:00:56 -0700 | [diff] [blame] | 133 | memory_info_hob->EccSupport, |
| 134 | src_dimm->MfgId, |
| 135 | src_dimm->SpdModuleType); |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 136 | index++; |
| 137 | } |
| 138 | } |
| 139 | mem_info->dimm_cnt = index; |
| 140 | printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); |
| 141 | } |
| 142 | |
Aaron Durbin | 79f0741 | 2017-04-16 21:49:29 -0500 | [diff] [blame] | 143 | asmlinkage void car_stage_entry(void) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 144 | { |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 145 | bool s3wake; |
| 146 | struct postcar_frame pcf; |
| 147 | uintptr_t top_of_ram; |
| 148 | struct chipset_power_state *ps; |
| 149 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 150 | console_init(); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 151 | |
| 152 | /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ |
| 153 | systemagent_early_init(); |
| 154 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 155 | ps = pmc_get_power_state(); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 156 | timestamp_add_now(TS_START_ROMSTAGE); |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 157 | s3wake = pmc_fill_power_state(ps) == ACPI_S3; |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 158 | fsp_memory_init(s3wake); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 159 | pmc_set_disb(); |
Barnali Sarkar | b7fa7fb | 2017-02-10 21:36:58 +0530 | [diff] [blame] | 160 | if (!s3wake) |
| 161 | save_dimm_info(); |
Kyösti Mälkki | 6e2d0c1 | 2019-06-28 10:08:51 +0300 | [diff] [blame] | 162 | if (postcar_frame_init(&pcf, 0)) |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 163 | die("Unable to initialize postcar frame.\n"); |
| 164 | |
| 165 | /* |
| 166 | * We need to make sure ramstage will be run cached. At this |
| 167 | * point exact location of ramstage in cbmem is not known. |
| 168 | * Instruct postcar to cache 16 megs under cbmem top which is |
| 169 | * a safe bet to cover ramstage. |
| 170 | */ |
| 171 | top_of_ram = (uintptr_t) cbmem_top(); |
| 172 | printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); |
| 173 | top_of_ram -= 16*MiB; |
| 174 | postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); |
| 175 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 176 | if (CONFIG(HAVE_SMI_HANDLER)) { |
Kyösti Mälkki | 14222d8 | 2019-08-05 15:10:18 +0300 | [diff] [blame] | 177 | uintptr_t smm_base; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 178 | size_t smm_size; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 179 | |
| 180 | /* |
| 181 | * Cache the TSEG region at the top of ram. This region is |
| 182 | * not restricted to SMM mode until SMM has been relocated. |
| 183 | * By setting the region to cacheable it provides faster access |
| 184 | * when relocating the SMM handler as well as using the TSEG |
| 185 | * region for other purposes. |
| 186 | */ |
| 187 | smm_region(&smm_base, &smm_size); |
Kyösti Mälkki | 14222d8 | 2019-08-05 15:10:18 +0300 | [diff] [blame] | 188 | postcar_frame_add_mtrr(&pcf, smm_base, smm_size, |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 189 | MTRR_TYPE_WRBACK); |
| 190 | } |
| 191 | |
| 192 | /* Cache the ROM as WP just below 4GiB. */ |
Nico Huber | 6ea6775 | 2018-05-27 14:37:52 +0200 | [diff] [blame] | 193 | postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 194 | |
Aaron Durbin | 79f0741 | 2017-04-16 21:49:29 -0500 | [diff] [blame] | 195 | run_postcar_phase(&pcf); |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 196 | } |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 197 | |
Naresh G Solanki | 79239b7 | 2016-11-16 21:34:41 +0530 | [diff] [blame] | 198 | static void cpu_flex_override(FSP_M_CONFIG *m_cfg) |
| 199 | { |
| 200 | msr_t flex_ratio; |
| 201 | m_cfg->CpuRatioOverride = 1; |
| 202 | /* |
| 203 | * Set cpuratio to that value set in bootblock, This will ensure FSPM |
| 204 | * knows the intended flex ratio. |
| 205 | */ |
| 206 | flex_ratio = rdmsr(MSR_FLEX_RATIO); |
| 207 | m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; |
| 208 | } |
| 209 | |
Maxim Polyakov | 0220d1e | 2019-03-18 17:38:44 +0300 | [diff] [blame] | 210 | static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, |
| 211 | FSP_M_TEST_CONFIG *m_t_cfg, |
| 212 | const struct soc_intel_skylake_config *config) |
| 213 | { |
| 214 | const struct device *dev; |
| 215 | /* |
| 216 | * To enable or disable the corresponding PEG root port you need to |
| 217 | * add to the devicetree.cb: |
| 218 | * |
| 219 | * device pci 01.0 on end # enable PEG0 root port |
| 220 | * device pci 01.1 off end # do not configure PEG1 |
| 221 | * |
| 222 | * If PEG port is not defined in the device tree, it will be disabled |
| 223 | * in FSP |
| 224 | */ |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 225 | dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ |
Maxim Polyakov | 0220d1e | 2019-03-18 17:38:44 +0300 | [diff] [blame] | 226 | if (!dev || !dev->enabled) |
| 227 | m_cfg->Peg0Enable = 0; |
| 228 | else if (dev->enabled) { |
| 229 | m_cfg->Peg0Enable = dev->enabled; |
| 230 | m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth; |
| 231 | /* Use maximum possible link speed */ |
| 232 | m_cfg->Peg0MaxLinkSpeed = 0; |
| 233 | /* Power down unused lanes based on the max possible width */ |
| 234 | m_cfg->Peg0PowerDownUnusedLanes = 1; |
| 235 | /* Set [Auto] for options to enable equalization methods */ |
| 236 | m_t_cfg->Peg0Gen3EqPh2Enable = 2; |
| 237 | m_t_cfg->Peg0Gen3EqPh3Method = 0; |
| 238 | } |
| 239 | |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 240 | dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */ |
Maxim Polyakov | 0220d1e | 2019-03-18 17:38:44 +0300 | [diff] [blame] | 241 | if (!dev || !dev->enabled) |
| 242 | m_cfg->Peg1Enable = 0; |
| 243 | else if (dev->enabled) { |
| 244 | m_cfg->Peg1Enable = dev->enabled; |
| 245 | m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth; |
| 246 | m_cfg->Peg1MaxLinkSpeed = 0; |
| 247 | m_cfg->Peg1PowerDownUnusedLanes = 1; |
| 248 | m_t_cfg->Peg1Gen3EqPh2Enable = 2; |
| 249 | m_t_cfg->Peg1Gen3EqPh3Method = 0; |
| 250 | } |
| 251 | |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 252 | dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */ |
Maxim Polyakov | 0220d1e | 2019-03-18 17:38:44 +0300 | [diff] [blame] | 253 | if (!dev || !dev->enabled) |
| 254 | m_cfg->Peg2Enable = 0; |
| 255 | else if (dev->enabled) { |
| 256 | m_cfg->Peg2Enable = dev->enabled; |
| 257 | m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth; |
| 258 | m_cfg->Peg2MaxLinkSpeed = 0; |
| 259 | m_cfg->Peg2PowerDownUnusedLanes = 1; |
| 260 | m_t_cfg->Peg2Gen3EqPh2Enable = 2; |
| 261 | m_t_cfg->Peg2Gen3EqPh3Method = 0; |
| 262 | } |
| 263 | } |
| 264 | |
Aamir Bohra | 6375512 | 2017-02-06 21:48:48 +0530 | [diff] [blame] | 265 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, |
| 266 | const struct soc_intel_skylake_config *config) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 267 | { |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 268 | int i; |
| 269 | uint32_t mask = 0; |
| 270 | |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 271 | m_cfg->MmioSize = 0x800; /* 2GB in MB */ |
| 272 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 273 | m_cfg->IedSize = CONFIG_IED_REGION_SIZE; |
| 274 | m_cfg->ProbelessTrace = config->ProbelessTrace; |
Subrata Banik | 3214bc4 | 2017-07-10 13:17:09 +0530 | [diff] [blame] | 275 | m_cfg->SaGv = config->SaGv; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 276 | m_cfg->UserBd = BOARD_TYPE_ULT_ULX; |
| 277 | m_cfg->RMT = config->Rmt; |
Shaunak Saha | ef250c4 | 2018-08-31 12:49:08 -0700 | [diff] [blame] | 278 | m_cfg->CmdTriStateDis = config->CmdTriStateDis; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 279 | m_cfg->DdrFreqLimit = config->DdrFreqLimit; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 280 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
Robbie Zhang | e65affa | 2017-02-13 12:07:53 -0800 | [diff] [blame] | 281 | m_cfg->PrmrrSize = config->PrmrrSize; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 282 | for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { |
| 283 | if (config->PcieRpEnable[i]) |
| 284 | mask |= (1<<i); |
| 285 | } |
| 286 | m_cfg->PcieRpEnableMask = mask; |
Naresh G Solanki | 79239b7 | 2016-11-16 21:34:41 +0530 | [diff] [blame] | 287 | |
| 288 | cpu_flex_override(m_cfg); |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 289 | |
| 290 | if (!config->ignore_vtd) { |
| 291 | m_cfg->PchHpetBdfValid = 1; |
| 292 | m_cfg->PchHpetBusNumber = 250; |
| 293 | m_cfg->PchHpetDeviceNumber = 15; |
| 294 | m_cfg->PchHpetFunctionNumber = 0; |
| 295 | } |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 296 | } |
| 297 | |
Maxim Polyakov | de08ae1 | 2019-03-21 18:50:42 +0300 | [diff] [blame] | 298 | static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, |
| 299 | const struct soc_intel_skylake_config *config) |
| 300 | { |
| 301 | const struct device *dev; |
| 302 | |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 303 | dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Maxim Polyakov | de08ae1 | 2019-03-21 18:50:42 +0300 | [diff] [blame] | 304 | if (!dev || !dev->enabled) { |
| 305 | /* |
| 306 | * If iGPU is disabled or not defined in the devicetree.cb, |
| 307 | * the FSP does not initialize this device |
| 308 | */ |
| 309 | m_cfg->InternalGfx = 0; |
Maxim Polyakov | 5806665 | 2019-04-25 12:32:15 +0300 | [diff] [blame] | 310 | m_cfg->IgdDvmt50PreAlloc = 0; |
Maxim Polyakov | de08ae1 | 2019-03-21 18:50:42 +0300 | [diff] [blame] | 311 | } else { |
| 312 | m_cfg->InternalGfx = 1; |
Maxim Polyakov | 5806665 | 2019-04-25 12:32:15 +0300 | [diff] [blame] | 313 | /* |
| 314 | * Set IGD stolen size to 64MB. The FBC hardware for skylake |
| 315 | * does not have access to the bios_reserved range so it always |
| 316 | * assumes 8MB is used and so the kernel will avoid the last |
| 317 | * 8MB of the stolen window. With the default stolen size of |
| 318 | * 32MB(-8MB) there is not enough space for FBC to work with |
| 319 | * a high resolution panel |
| 320 | */ |
| 321 | m_cfg->IgdDvmt50PreAlloc = 2; |
Maxim Polyakov | de08ae1 | 2019-03-21 18:50:42 +0300 | [diff] [blame] | 322 | } |
Maxim Polyakov | 3ba3807 | 2019-05-06 12:07:24 +0300 | [diff] [blame] | 323 | m_cfg->PrimaryDisplay = config->PrimaryDisplay; |
Maxim Polyakov | de08ae1 | 2019-03-21 18:50:42 +0300 | [diff] [blame] | 324 | } |
| 325 | |
Andrey Petrov | f796c6e | 2016-11-18 14:57:51 -0800 | [diff] [blame] | 326 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 327 | { |
Aamir Bohra | 6375512 | 2017-02-06 21:48:48 +0530 | [diff] [blame] | 328 | const struct soc_intel_skylake_config *config; |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 329 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 330 | FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 331 | |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 332 | config = config_of_path(PCH_DEVFN_LPC); |
Aamir Bohra | 6375512 | 2017-02-06 21:48:48 +0530 | [diff] [blame] | 333 | |
| 334 | soc_memory_init_params(m_cfg, config); |
Maxim Polyakov | 0220d1e | 2019-03-18 17:38:44 +0300 | [diff] [blame] | 335 | soc_peg_init_params(m_cfg, m_t_cfg, config); |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 336 | |
Duncan Laurie | e0b5795 | 2017-08-10 16:27:48 -0700 | [diff] [blame] | 337 | /* Skip creating Management Engine MBP HOB */ |
| 338 | m_t_cfg->SkipMbpHob = 0x01; |
| 339 | |
Barnali Sarkar | 5bf42c6 | 2016-08-24 20:48:46 +0530 | [diff] [blame] | 340 | /* Enable DMI Virtual Channel for ME */ |
| 341 | m_t_cfg->DmiVcm = 0x01; |
| 342 | |
| 343 | /* Enable Sending DID to ME */ |
| 344 | m_t_cfg->SendDidMsg = 0x01; |
| 345 | m_t_cfg->DidInitStat = 0x01; |
| 346 | |
Aamir Bohra | 6375512 | 2017-02-06 21:48:48 +0530 | [diff] [blame] | 347 | /* DCI and TraceHub configs */ |
| 348 | m_t_cfg->PchDciEn = config->PchDciEn; |
| 349 | m_cfg->EnableTraceHub = config->EnableTraceHub; |
| 350 | m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; |
| 351 | m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; |
| 352 | |
Naresh G Solanki | ff48b3b | 2017-07-12 23:01:26 +0530 | [diff] [blame] | 353 | /* Enable SMBus controller based on config */ |
| 354 | m_cfg->SmbusEnable = config->SmbusEnable; |
| 355 | |
Maxim Polyakov | de08ae1 | 2019-03-21 18:50:42 +0300 | [diff] [blame] | 356 | /* Set primary graphic device */ |
| 357 | soc_primary_gfx_config_params(m_cfg, config); |
Maxim Polyakov | a12e9b0 | 2019-04-03 11:21:17 +0300 | [diff] [blame] | 358 | m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; |
Maxim Polyakov | de08ae1 | 2019-03-21 18:50:42 +0300 | [diff] [blame] | 359 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 360 | mainboard_memory_init_params(mupd); |
| 361 | } |
| 362 | |
Pratik Prajapati | ffc934d | 2016-11-18 14:36:34 -0800 | [diff] [blame] | 363 | void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, |
| 364 | struct mma_config_param *mma_cfg) |
| 365 | { |
| 366 | /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 367 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Pratik Prajapati | ffc934d | 2016-11-18 14:36:34 -0800 | [diff] [blame] | 368 | |
| 369 | memory_cfg->MmaTestContentPtr = |
| 370 | (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); |
| 371 | memory_cfg->MmaTestContentSize = |
| 372 | region_device_sz(&mma_cfg->test_content); |
| 373 | memory_cfg->MmaTestConfigPtr = |
| 374 | (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); |
| 375 | memory_cfg->MmaTestConfigSize = |
| 376 | region_device_sz(&mma_cfg->test_param); |
| 377 | memory_cfg->MrcFastBoot = 0x00; |
| 378 | memory_cfg->SaGv = 0x02; |
| 379 | } |
| 380 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 381 | __weak void mainboard_memory_init_params(FSPM_UPD *mupd) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 382 | { |
| 383 | /* Do nothing */ |
| 384 | } |