blob: 4160479b8da8d8a07cf81f46748f26808dd50007 [file] [log] [blame]
Stefan Reinauere1ae4b22012-04-27 23:20:58 +02001chip northbridge/intel/sandybridge
2
3 # Enable DisplayPort 1 Hotplug with 6ms pulse
4 register "gpu_dp_d_hotplug" = "0x06"
5
6 # Enable DisplayPort 0 Hotplug with 6ms pulse
7 register "gpu_dp_c_hotplug" = "0x06"
8
9 # Enable DVI Hotplug with 6ms pulse
10 register "gpu_dp_b_hotplug" = "0x06"
11
Keith Hui45e4ab42023-07-22 12:49:05 -040012 register "spd_addresses" = "{0x50, 0, 0x52, 0}"
Vladimir Serbinenkod2990c92016-02-10 02:52:42 +010013 register "max_mem_clock_mhz" = "666"
14
Arthur Heymanscdb26fd2021-11-15 20:12:02 +010015 chip cpu/intel/model_206ax
16 device cpu_cluster 0 on end
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020017
Arthur Heymanscdb26fd2021-11-15 20:12:02 +010018 register "acpi_c1" = "CPU_ACPI_C3"
19 register "acpi_c2" = "CPU_ACPI_C6"
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020020 end
21
Stefan Reinauer4aff4452013-02-12 14:17:15 -080022 device domain 0 on
Stefan Reinauer56c7dc72012-05-15 12:36:57 -070023 subsystemid 0x1ae0 0xc000 inherit
Arthur Heymansb5df65a2022-11-12 14:51:49 +010024 device ref host_bridge on end # host bridge
25 device ref igd on end # vga controller
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020026
27 chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020028 # GPI routing
29 # 0 No effect (default)
30 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
31 # 2 SCI (if corresponding GPIO_EN bit is also set)
32 register "gpi1_routing" = "0"
33 register "gpi14_routing" = "2"
34
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020035 register "sata_port_map" = "0x3"
36
Arthur Heymans6beaef92019-06-16 23:29:23 +020037 register "gen1_dec" = "0x00fc1601"
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020038 # SuperIO range is 0x700-0x73f
39 register "gen2_dec" = "0x003c0701"
40
Keith Hui51a57eb2024-02-05 16:44:38 -050041 register "usb_port_config" = "{
42 { 1, 1, 0 }, /* P0: Front port (OC0) */
43 { 1, 0, 1 }, /* P1: Back port (OC1) */
44 { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
45 { 1, 0, -1 }, /* P3: MMC (no OC) */
46 { 1, 1, 2 }, /* P4: Front port (OC2) */
47 { 0, 0, -1 }, /* P5: Empty */
48 { 0, 0, -1 }, /* P6: Empty */
49 { 0, 0, -1 }, /* P7: Empty */
50 { 1, 0, 4 }, /* P8: Back port (OC4) */
51 { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */
52 { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */
53 { 0, 0, -1 }, /* P11: Empty */
54 { 1, 0, 6 }, /* P12: Back port (OC6) */
55 { 1, 0, 5 }, /* P13: Back port (OC5) */
56 }"
57
Arthur Heymansb5df65a2022-11-12 14:51:49 +010058 device ref mei1 on end # Management Engine Interface 1
59 device ref mei2 off end # Management Engine Interface 2
60 device ref me_ide_r off end # Management Engine IDE-R
61 device ref me_kt off end # Management Engine KT
62 device ref gbe off end # Intel Gigabit Ethernet
63 device ref ehci2 on end # USB2 EHCI #2
64 device ref hda on end # High Definition Audio
65 device ref pcie_rp1 on end # PCIe Port #1 (WLAN)
66 device ref pcie_rp2 off end # PCIe Port #2
67 device ref pcie_rp3 on end # PCIe Port #3 (Debug)
68 device ref pcie_rp4 on end # PCIe Port #4 (LAN)
69 device ref pcie_rp5 off end # PCIe Port #5
70 device ref pcie_rp6 off end # PCIe Port #6
71 device ref pcie_rp7 off end # PCIe Port #7
72 device ref pcie_rp8 off end # PCIe Port #8
73 device ref ehci1 on end # USB2 EHCI #1
74 device ref pci_bridge off end # PCI bridge
75 device ref lpc on # LPC bridge
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020076 chip superio/ite/it8772f
77 # Enable GPIO10 as USBPWRON12#
78 # Enable GPIO12 as USBPWRON13#
79 register "gpio_set1" = "0x05"
80 # Enable GPIO22 as SIO_WAEKSCI#
81 register "gpio_set2" = "0x04"
82 # Enable GPIO32 as SIO_EXTSMI#
83 register "gpio_set3" = "0x04"
84 # Enable GPIO45 as LED_POWER#
85 register "gpio_set4" = "0x20"
86 # Enable GPIO51 as USBPWRON8#
87 # Enable GPIO52 as USBPWRON1#
88 register "gpio_set5" = "0x06"
89 # Skip keyboard init
Elyes Haouas7bde4e82022-12-02 08:42:04 +010090 register "skip_keyboard" = "true"
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020091 # Enable PECI on TMPIN3
Joel Linnfb516612024-03-29 14:08:35 +010092 register "TMPIN3.mode" = "THERMAL_PECI"
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020093 # Enable FAN3
Joel Linnfb516612024-03-29 14:08:35 +010094 register "FAN3.mode" = "FAN_SMART_SOFTWARE"
Matt DeVillierb40b6ff2024-03-25 10:14:15 -050095 register "FAN3.smart.pwm_start" = "30"
Stefan Reinauere1ae4b22012-04-27 23:20:58 +020096
97 device pnp 2e.0 off end # FDC
98 device pnp 2e.1 on # Serial Port 1
99 io 0x60 = 0x2f8
100 irq 0x70 = 4
101 end
102 device pnp 2e.4 on # Environment Controller
103 io 0x60 = 0x700
104 io 0x62 = 0x710
105 end
106 device pnp 2e.7 on # GPIO
107 io 0x60 = 0x720
108 io 0x62 = 0x730
109 end
110 device pnp 2e.5 on
111 io 0x60 = 0x60
112 io 0x62 = 0x64
113 irq 0x70 = 1
114 end # Keyboard
115 device pnp 2e.6 on
116 irq 0x70 = 12
117 end # Mouse
118 device pnp 2e.a off end # IR
119 end
Matt DeVillier3044af72018-08-01 13:05:14 -0500120 chip drivers/pc80/tpm
121 device pnp 0c31.0 on end
122 end
Stefan Reinauere1ae4b22012-04-27 23:20:58 +0200123 end
Arthur Heymansb5df65a2022-11-12 14:51:49 +0100124 device ref sata1 on end # SATA Controller 1
125 device ref smbus on end # SMBus
126 device ref sata2 off end # SATA Controller 2
127 device ref thermal on end # Thermal
Stefan Reinauere1ae4b22012-04-27 23:20:58 +0200128 end
129 end
130end