blob: b791cbc77285a56f7f19118720b869734d0c6b7f [file] [log] [blame]
Angel Pons7544e2f2020-04-03 01:23:10 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Dennis Wassenbergbd105162015-09-10 12:20:58 +02002
Felix Held972d9f22022-02-23 16:32:20 +01003#include <arch/hpet.h>
Arthur Heymansfa5d0f82019-11-12 19:11:50 +01004#include <bootblock_common.h>
Dennis Wassenbergbd105162015-09-10 12:20:58 +02005#include <stdint.h>
Kyösti Mälkki3855c012019-03-03 08:45:19 +02006#include <device/pnp_ops.h>
Dennis Wassenbergbd105162015-09-10 12:20:58 +02007#include <device/pnp.h>
8#include <northbridge/intel/sandybridge/raminit.h>
Dennis Wassenbergbd105162015-09-10 12:20:58 +02009#include <southbridge/intel/bd82x6x/pch.h>
10#include <superio/ite/it8783ef/it8783ef.h>
11#include <superio/ite/common/ite.h>
12
Arthur Heymansfa5d0f82019-11-12 19:11:50 +010013void bootblock_mainboard_early_init(void)
Dennis Wassenbergbd105162015-09-10 12:20:58 +020014{
15 const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO);
16
17 pnp_enter_conf_state(dev);
18 pnp_set_logical_device(dev);
19
20 pnp_write_config(dev, 0x23, ITE_UART_CLK_PREDIVIDE_24);
21
22 /* Switch multi function for UART4 */
23 pnp_write_config(dev, 0x2a, 0x04);
24 /* Switch multi function for UART3 */
25 pnp_write_config(dev, 0x2c, 0x13);
26
27 /* No GPIOs used: Clear any output / pull-up that's set by default */
28 pnp_write_config(dev, 0xb8, 0x00);
29 pnp_write_config(dev, 0xc0, 0x00);
30 pnp_write_config(dev, 0xc3, 0x00);
31 pnp_write_config(dev, 0xc8, 0x00);
32 pnp_write_config(dev, 0xcb, 0x00);
33 pnp_write_config(dev, 0xef, 0x00);
34
35 pnp_exit_conf_state(dev);
36}
37
Keith Hui45e4ab42023-07-22 12:49:05 -040038void mainboard_fill_pei_data(struct pei_data *pei_data)
Dennis Wassenbergbd105162015-09-10 12:20:58 +020039{
Keith Hui7039edd2023-07-21 10:12:05 -040040 /* TODO: Confirm if need to enable peg10 in devicetree */
41 pei_data->pcie_init = 1;
Dennis Wassenbergbd105162015-09-10 12:20:58 +020042}