| Angel Pons | 5f1bf2f | 2020-04-03 01:21:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Angel Pons | ffcf641 | 2020-03-05 01:30:49 +0100 | [diff] [blame] | 2 | |
| 3 | #include <bootblock_common.h> |
| 4 | #include <device/pnp_ops.h> |
| Angel Pons | ffcf641 | 2020-03-05 01:30:49 +0100 | [diff] [blame] | 5 | #include <southbridge/intel/bd82x6x/pch.h> |
| 6 | #include <superio/nuvoton/common/nuvoton.h> |
| 7 | #include <superio/nuvoton/nct6779d/nct6779d.h> |
| 8 | |
| 9 | #define GLOBAL_DEV PNP_DEV(0x2e, 0) |
| 10 | #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) |
| 11 | #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) |
| 12 | |
| Angel Pons | ffcf641 | 2020-03-05 01:30:49 +0100 | [diff] [blame] | 13 | void bootblock_mainboard_early_init(void) |
| 14 | { |
| 15 | nuvoton_pnp_enter_conf_state(GLOBAL_DEV); |
| 16 | |
| 17 | /* Select SIO pin states */ |
| 18 | pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); |
| 19 | pnp_write_config(GLOBAL_DEV, 0x1b, 0x70); |
| 20 | pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); |
| 21 | pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); |
| 22 | pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); |
| 23 | pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); |
| 24 | pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); |
| 25 | |
| 26 | /* Power RAM in S3 */ |
| 27 | pnp_set_logical_device(ACPI_DEV); |
| 28 | pnp_write_config(ACPI_DEV, 0xe4, 0x10); |
| 29 | |
| 30 | nuvoton_pnp_exit_conf_state(GLOBAL_DEV); |
| 31 | |
| 32 | /* Enable UART */ |
| 33 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 34 | } |