| Angel Pons | ffcf641 | 2020-03-05 01:30:49 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation; version 2 of |
| 7 | * the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <bootblock_common.h> |
| 16 | #include <device/pnp_ops.h> |
| 17 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 18 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 19 | #include <southbridge/intel/bd82x6x/pch.h> |
| 20 | #include <superio/nuvoton/common/nuvoton.h> |
| 21 | #include <superio/nuvoton/nct6779d/nct6779d.h> |
| 22 | |
| 23 | #define GLOBAL_DEV PNP_DEV(0x2e, 0) |
| 24 | #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) |
| 25 | #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) |
| 26 | |
| 27 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 28 | { 1, 0, 0 }, |
| 29 | { 1, 0, 0 }, |
| 30 | { 1, 0, 1 }, |
| 31 | { 1, 0, 1 }, |
| 32 | { 1, 0, 2 }, |
| 33 | { 1, 0, 2 }, |
| 34 | { 1, 0, 3 }, |
| 35 | { 1, 0, 3 }, |
| 36 | { 1, 0, 4 }, |
| 37 | { 1, 0, 4 }, |
| 38 | { 1, 0, 6 }, |
| 39 | { 1, 0, 5 }, |
| 40 | { 1, 0, 5 }, |
| 41 | { 1, 0, 6 }, |
| 42 | }; |
| 43 | |
| 44 | void bootblock_mainboard_early_init(void) |
| 45 | { |
| 46 | nuvoton_pnp_enter_conf_state(GLOBAL_DEV); |
| 47 | |
| 48 | /* Select SIO pin states */ |
| 49 | pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); |
| 50 | pnp_write_config(GLOBAL_DEV, 0x1b, 0x70); |
| 51 | pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); |
| 52 | pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); |
| 53 | pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); |
| 54 | pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); |
| 55 | pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); |
| 56 | |
| 57 | /* Power RAM in S3 */ |
| 58 | pnp_set_logical_device(ACPI_DEV); |
| 59 | pnp_write_config(ACPI_DEV, 0xe4, 0x10); |
| 60 | |
| 61 | nuvoton_pnp_exit_conf_state(GLOBAL_DEV); |
| 62 | |
| 63 | /* Enable UART */ |
| 64 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 65 | } |
| 66 | |
| 67 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 68 | { |
| 69 | read_spd(&spd[0], 0x50, id_only); |
| 70 | read_spd(&spd[1], 0x51, id_only); |
| 71 | read_spd(&spd[2], 0x52, id_only); |
| 72 | read_spd(&spd[3], 0x53, id_only); |
| 73 | } |