Ronald G. Minnich | f89e6b2 | 2012-12-10 16:13:43 -0800 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Ronald G. Minnich | f89e6b2 | 2012-12-10 16:13:43 -0800 | [diff] [blame] | 3 | * |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 4 | * Copyright 2013 Google Inc. |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Ronald G. Minnich | f89e6b2 | 2012-12-10 16:13:43 -0800 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | f89e6b2 | 2012-12-10 16:13:43 -0800 | [diff] [blame] | 18 | */ |
| 19 | |
David Hendricks | 50c0a50 | 2013-01-31 17:05:50 -0800 | [diff] [blame] | 20 | #include <console/console.h> |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/i2c.h> |
| 23 | #include <drivers/ti/tps65090/tps65090.h> |
| 24 | #include <cbmem.h> |
| 25 | #include <delay.h> |
| 26 | #include <edid.h> |
| 27 | #include <vbe.h> |
| 28 | #include <boot/coreboot_tables.h> |
| 29 | #include <arch/cache.h> |
| 30 | #include <arch/exception.h> |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 31 | #include <cpu/samsung/exynos5250/tmu.h> |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 32 | #include <cpu/samsung/exynos5250/clk.h> |
| 33 | #include <cpu/samsung/exynos5250/cpu.h> |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 34 | #include <cpu/samsung/exynos5250/gpio.h> |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 35 | #include <cpu/samsung/exynos5250/power.h> |
Stefan Reinauer | b98dec0 | 2013-05-14 13:32:33 -0700 | [diff] [blame] | 36 | #include <cpu/samsung/exynos5250/i2c.h> |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 37 | #include <cpu/samsung/exynos5250/dp-core.h> |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 38 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 39 | #include "exynos5250.h" |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 40 | |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 41 | /* convenient shorthand (in MB) */ |
| 42 | #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) |
| 43 | #define DRAM_SIZE CONFIG_DRAM_SIZE_MB |
| 44 | #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ |
| 45 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 46 | static struct edid edid = { |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 47 | .ha = 1366, |
| 48 | .va = 768, |
| 49 | .bpp = 16, |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 50 | }; |
| 51 | |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 52 | /* TODO: transplanted DP stuff, clean up once we have something that works */ |
| 53 | static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ |
| 54 | static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ |
| 55 | static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ |
| 56 | |
| 57 | static void exynos_dp_bridge_setup(void) |
Ronald G. Minnich | f89e6b2 | 2012-12-10 16:13:43 -0800 | [diff] [blame] | 58 | { |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 59 | exynos_pinmux_config(PERIPH_ID_DPHPD, 0); |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 60 | |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 61 | gpio_set_value(dp_pd_l, 1); |
Stefan Reinauer | dc006c1 | 2013-05-15 14:54:07 -0700 | [diff] [blame] | 62 | gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT); |
| 63 | gpio_set_pull(dp_pd_l, GPIO_PULL_NONE); |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 64 | |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 65 | gpio_set_value(dp_rst_l, 0); |
Stefan Reinauer | dc006c1 | 2013-05-15 14:54:07 -0700 | [diff] [blame] | 66 | gpio_cfg_pin(dp_rst_l, GPIO_OUTPUT); |
| 67 | gpio_set_pull(dp_rst_l, GPIO_PULL_NONE); |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 68 | udelay(10); |
| 69 | gpio_set_value(dp_rst_l, 1); |
Ronald G. Minnich | f89e6b2 | 2012-12-10 16:13:43 -0800 | [diff] [blame] | 70 | } |
| 71 | |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 72 | static void exynos_dp_bridge_init(void) |
| 73 | { |
| 74 | /* De-assert PD (and possibly RST) to power up the bridge */ |
| 75 | gpio_set_value(dp_pd_l, 1); |
| 76 | gpio_set_value(dp_rst_l, 1); |
| 77 | |
| 78 | /* |
| 79 | * We need to wait for 90ms after bringing up the bridge since |
| 80 | * there is a phantom "high" on the HPD chip during its |
| 81 | * bootup. The phantom high comes within 7ms of de-asserting |
| 82 | * PD and persists for at least 15ms. The real high comes |
| 83 | * roughly 50ms after PD is de-asserted. The phantom high |
| 84 | * makes it hard for us to know when the NXP chip is up. |
| 85 | */ |
| 86 | udelay(90000); |
| 87 | } |
| 88 | |
| 89 | static int exynos_dp_hotplug(void) |
| 90 | { |
| 91 | /* Check HPD. If it's high, we're all good. */ |
| 92 | return gpio_get_value(dp_hpd) ? 0 : 1; |
| 93 | } |
| 94 | |
| 95 | static void exynos_dp_reset(void) |
| 96 | { |
| 97 | gpio_set_value(dp_pd_l, 0); |
| 98 | gpio_set_value(dp_rst_l, 0); |
| 99 | /* paranoid delay period (300ms) */ |
| 100 | udelay(300 * 1000); |
| 101 | } |
| 102 | |
| 103 | /* |
| 104 | * This delay is T3 in the LCD timing spec (defined as >200ms). We set |
| 105 | * this down to 60ms since that's the approximate maximum amount of time |
| 106 | * it'll take a bridge to start outputting LVDS data. The delay of |
| 107 | * >200ms is just a conservative value to avoid turning on the backlight |
| 108 | * when there's random LCD data on the screen. Shaving 140ms off the |
| 109 | * boot is an acceptable trade-off. |
| 110 | */ |
| 111 | #define LCD_T3_DELAY_MS 60 |
| 112 | |
| 113 | #define LCD_T5_DELAY_MS 10 |
| 114 | #define LCD_T6_DELAY_MS 10 |
| 115 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 116 | static void backlight_pwm(void) |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 117 | { |
| 118 | /*Configure backlight PWM as a simple output high (100% brightness) */ |
| 119 | gpio_direction_output(GPIO_B20, 1); |
| 120 | udelay(LCD_T6_DELAY_MS * 1000); |
| 121 | } |
| 122 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 123 | static void backlight_en(void) |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 124 | { |
Stefan Reinauer | dc006c1 | 2013-05-15 14:54:07 -0700 | [diff] [blame] | 125 | /* Configure GPIO for LCD_BL_EN */ |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 126 | gpio_direction_output(GPIO_X30, 1); |
| 127 | } |
| 128 | |
| 129 | #define TPS69050_BUS 4 /* Snow-specific */ |
| 130 | |
| 131 | #define FET1_CTRL 0x0f |
| 132 | #define FET6_CTRL 0x14 |
| 133 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 134 | static void lcd_vdd(void) |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 135 | { |
| 136 | /* Enable FET6, lcd panel */ |
| 137 | tps65090_fet_enable(TPS69050_BUS, FET6_CTRL); |
| 138 | } |
| 139 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 140 | static void backlight_vdd(void) |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 141 | { |
| 142 | /* Enable FET1, backlight */ |
| 143 | tps65090_fet_enable(TPS69050_BUS, FET1_CTRL); |
| 144 | udelay(LCD_T5_DELAY_MS * 1000); |
| 145 | } |
| 146 | |
| 147 | //static struct video_info smdk5250_dp_config = { |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 148 | static struct video_info dp_video_info = { |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 149 | /* FIXME: fix video_info struct to use const for name */ |
| 150 | .name = (char *)"eDP-LVDS NXP PTN3460", |
| 151 | |
| 152 | .h_sync_polarity = 0, |
| 153 | .v_sync_polarity = 0, |
| 154 | .interlaced = 0, |
| 155 | |
| 156 | .color_space = COLOR_RGB, |
| 157 | .dynamic_range = VESA, |
| 158 | .ycbcr_coeff = COLOR_YCBCR601, |
| 159 | .color_depth = COLOR_8, |
| 160 | |
| 161 | .link_rate = LINK_RATE_2_70GBPS, |
| 162 | .lane_count = LANE_COUNT2, |
| 163 | }; |
| 164 | |
| 165 | /* FIXME: move some place more appropriate */ |
| 166 | #define EXYNOS5250_DP1_BASE 0x145b0000 |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 167 | #define MAX_DP_TRIES 5 |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 168 | |
| 169 | /* |
| 170 | * This function disables the USB3.0 PLL to save power |
| 171 | */ |
| 172 | static void disable_usb30_pll(void) |
| 173 | { |
| 174 | enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11; |
| 175 | |
| 176 | gpio_direction_output(usb3_pll_l, 0); |
| 177 | } |
| 178 | |
Gabe Black | 1387b43 | 2013-05-18 15:55:47 -0700 | [diff] [blame] | 179 | static void gpio_init(void) |
| 180 | { |
| 181 | /* Set up the I2C busses. */ |
| 182 | exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE); |
| 183 | exynos_pinmux_config(PERIPH_ID_I2C1, PINMUX_FLAG_NONE); |
| 184 | exynos_pinmux_config(PERIPH_ID_I2C2, PINMUX_FLAG_NONE); |
| 185 | exynos_pinmux_config(PERIPH_ID_I2C3, PINMUX_FLAG_NONE); |
| 186 | exynos_pinmux_config(PERIPH_ID_I2C4, PINMUX_FLAG_NONE); |
| 187 | exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE); |
| 188 | |
| 189 | /* Set up the GPIOs used to arbitrate for I2C bus 4. */ |
| 190 | gpio_set_pull(GPIO_F03, GPIO_PULL_NONE); |
| 191 | gpio_set_pull(GPIO_E04, GPIO_PULL_NONE); |
| 192 | gpio_direction_output(GPIO_F03, 1); |
| 193 | gpio_direction_input(GPIO_E04); |
| 194 | |
| 195 | /* Set up the GPIO used to enable the audio codec. */ |
| 196 | gpio_set_pull(GPIO_X17, GPIO_PULL_NONE); |
| 197 | gpio_set_pull(GPIO_X15, GPIO_PULL_NONE); |
| 198 | gpio_direction_output(GPIO_X17, 1); |
| 199 | gpio_direction_output(GPIO_X15, 1); |
| 200 | |
| 201 | /* Set up the I2S busses. */ |
| 202 | exynos_pinmux_config(PERIPH_ID_I2S1, PINMUX_FLAG_NONE); |
| 203 | } |
| 204 | |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 205 | /* this happens after cpu_init where exynos resources are set */ |
| 206 | static void mainboard_init(device_t dev) |
| 207 | { |
| 208 | int dp_tries; |
| 209 | struct s5p_dp_device dp_device = { |
| 210 | .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 211 | .video_info = &dp_video_info, |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 212 | }; |
| 213 | void *fb_addr; |
| 214 | |
Gabe Black | 1387b43 | 2013-05-18 15:55:47 -0700 | [diff] [blame] | 215 | gpio_init(); |
| 216 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 217 | i2c_init(TPS69050_BUS, I2C_0_SPEED, I2C_SLAVE); |
| 218 | i2c_init(7, I2C_0_SPEED, I2C_SLAVE); |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 219 | |
| 220 | tmu_init(&exynos5250_tmu_info); |
| 221 | |
| 222 | /* Clock Gating all the unused IP's to save power */ |
| 223 | clock_gate(); |
| 224 | |
| 225 | /* Disable USB3.0 PLL to save 250mW of power */ |
| 226 | disable_usb30_pll(); |
| 227 | |
| 228 | fb_addr = cbmem_find(CBMEM_ID_CONSOLE); |
Gabe Black | 1e797bd | 2013-05-18 15:58:46 -0700 | [diff] [blame] | 229 | set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 230 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 231 | lcd_vdd(); |
Stefan Reinauer | a86c33a | 2013-05-17 10:34:25 -0700 | [diff] [blame^] | 232 | |
| 233 | // FIXME: should timeout |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 234 | do { |
| 235 | udelay(50); |
| 236 | } while (!exynos_dp_hotplug()); |
| 237 | |
| 238 | exynos_dp_bridge_setup(); |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 239 | for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) { |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 240 | exynos_dp_bridge_init(); |
| 241 | if (exynos_dp_hotplug()) { |
| 242 | exynos_dp_reset(); |
| 243 | continue; |
| 244 | } |
| 245 | |
| 246 | if (dp_controller_init(&dp_device)) |
| 247 | continue; |
| 248 | |
| 249 | udelay(LCD_T3_DELAY_MS * 1000); |
| 250 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 251 | backlight_vdd(); |
| 252 | backlight_pwm(); |
| 253 | backlight_en(); |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 254 | /* if we're here, we're successful */ |
| 255 | break; |
| 256 | } |
| 257 | |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 258 | if (dp_tries > MAX_DP_TRIES) |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 259 | printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__); |
Stefan Reinauer | dc006c1 | 2013-05-15 14:54:07 -0700 | [diff] [blame] | 260 | |
Stefan Reinauer | a86c33a | 2013-05-17 10:34:25 -0700 | [diff] [blame^] | 261 | // Uncomment to get excessive GPIO output: |
| 262 | // gpio_info(); |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | static void mainboard_enable(device_t dev) |
| 266 | { |
| 267 | dev->ops->init = &mainboard_init; |
| 268 | |
| 269 | /* set up coreboot tables */ |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 270 | /* FIXME: this should happen somewhere else */ |
Stefan Reinauer | 2ae6d6f | 2013-05-09 16:16:13 -0700 | [diff] [blame] | 271 | high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; |
| 272 | high_tables_base = CONFIG_SYS_SDRAM_BASE + |
| 273 | ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - |
| 274 | CONFIG_COREBOOT_TABLES_SIZE; |
| 275 | cbmem_init(high_tables_base, high_tables_size); |
| 276 | |
| 277 | /* set up dcache and MMU */ |
| 278 | /* FIXME: this should happen via resource allocator */ |
| 279 | exynos5250_config_l2_cache(); |
| 280 | mmu_init(); |
| 281 | mmu_config_range(0, DRAM_START, DCACHE_OFF); |
| 282 | mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); |
| 283 | mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); |
| 284 | dcache_invalidate_all(); |
| 285 | dcache_mmu_enable(); |
| 286 | |
| 287 | /* this is going to move, but we must have it now and we're |
| 288 | * not sure where */ |
| 289 | exception_init(); |
| 290 | |
| 291 | const unsigned epll_hz = 192000000; |
| 292 | const unsigned sample_rate = 48000; |
| 293 | const unsigned lr_frame_size = 256; |
| 294 | clock_epll_set_rate(epll_hz); |
| 295 | clock_select_i2s_clk_source(); |
| 296 | clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); |
| 297 | |
| 298 | power_enable_xclkout(); |
| 299 | } |
| 300 | |
Ronald G. Minnich | f89e6b2 | 2012-12-10 16:13:43 -0800 | [diff] [blame] | 301 | struct chip_operations mainboard_ops = { |
Paul Menzel | 7df4ec0 | 2013-02-12 13:12:51 +0100 | [diff] [blame] | 302 | .name = "Samsung/Google ARM Chromebook", |
Ronald G. Minnich | f89e6b2 | 2012-12-10 16:13:43 -0800 | [diff] [blame] | 303 | .enable_dev = mainboard_enable, |
| 304 | }; |