snow: Make coreboot set up pins for busses it knows are hooked up as such
Coreboot knows that, for the snow board, certain pins are to be connected to
bus controllers in the SOC and to the wires of a bus external to the SOC. It
can configure them as such and free its payload from having to know how to
set everything up.
Change-Id: I1bb127c810e9ee077afc4227a6f316eaa53d6498
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3650
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index 250b71fd..2dd56fc 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -176,6 +176,32 @@
gpio_direction_output(usb3_pll_l, 0);
}
+static void gpio_init(void)
+{
+ /* Set up the I2C busses. */
+ exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C1, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C2, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C3, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C4, PINMUX_FLAG_NONE);
+ exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
+
+ /* Set up the GPIOs used to arbitrate for I2C bus 4. */
+ gpio_set_pull(GPIO_F03, GPIO_PULL_NONE);
+ gpio_set_pull(GPIO_E04, GPIO_PULL_NONE);
+ gpio_direction_output(GPIO_F03, 1);
+ gpio_direction_input(GPIO_E04);
+
+ /* Set up the GPIO used to enable the audio codec. */
+ gpio_set_pull(GPIO_X17, GPIO_PULL_NONE);
+ gpio_set_pull(GPIO_X15, GPIO_PULL_NONE);
+ gpio_direction_output(GPIO_X17, 1);
+ gpio_direction_output(GPIO_X15, 1);
+
+ /* Set up the I2S busses. */
+ exynos_pinmux_config(PERIPH_ID_I2S1, PINMUX_FLAG_NONE);
+}
+
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
@@ -186,6 +212,8 @@
};
void *fb_addr;
+ gpio_init();
+
i2c_init(TPS69050_BUS, I2C_0_SPEED, I2C_SLAVE);
i2c_init(7, I2C_0_SPEED, I2C_SLAVE);