arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 1 | uses HAVE_MP_TABLE |
| 2 | uses HAVE_PIRQ_TABLE |
| 3 | uses USE_FALLBACK_IMAGE |
| 4 | uses HAVE_FALLBACK_BOOT |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 5 | uses USE_FAILOVER_IMAGE |
| 6 | uses HAVE_FAILOVER_BOOT |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 7 | uses HAVE_HARD_RESET |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 8 | uses IRQ_SLOT_COUNT |
| 9 | uses HAVE_OPTION_TABLE |
| 10 | uses CONFIG_MAX_CPUS |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 11 | uses CONFIG_MAX_PHYSICAL_CPUS |
| 12 | uses CONFIG_LOGICAL_CPUS |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 13 | uses CONFIG_IOAPIC |
| 14 | uses CONFIG_SMP |
| 15 | uses FALLBACK_SIZE |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 16 | uses FAILOVER_SIZE |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 17 | uses ROM_SIZE |
| 18 | uses ROM_SECTION_SIZE |
| 19 | uses ROM_IMAGE_SIZE |
| 20 | uses ROM_SECTION_SIZE |
| 21 | uses ROM_SECTION_OFFSET |
Ed Swierk | be13dc7 | 2006-12-15 12:56:28 +0000 | [diff] [blame] | 22 | uses CONFIG_ROM_PAYLOAD |
| 23 | uses CONFIG_ROM_PAYLOAD_START |
Ed Swierk | 1a7a5b4 | 2006-12-15 11:42:16 +0000 | [diff] [blame] | 24 | uses CONFIG_COMPRESSED_PAYLOAD_LZMA |
Myles Watson | 15674b7 | 2007-12-09 17:18:29 +0000 | [diff] [blame] | 25 | uses CONFIG_PRECOMPRESSED_PAYLOAD |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 26 | uses PAYLOAD_SIZE |
| 27 | uses _ROMBASE |
| 28 | uses XIP_ROM_SIZE |
| 29 | uses XIP_ROM_BASE |
| 30 | uses STACK_SIZE |
| 31 | uses HEAP_SIZE |
| 32 | uses USE_OPTION_TABLE |
| 33 | uses LB_CKS_RANGE_START |
| 34 | uses LB_CKS_RANGE_END |
| 35 | uses LB_CKS_LOC |
| 36 | uses MAINBOARD |
| 37 | uses MAINBOARD_PART_NUMBER |
| 38 | uses MAINBOARD_VENDOR |
| 39 | uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID |
Myles Watson | a67c354c | 2008-09-18 15:30:42 +0000 | [diff] [blame^] | 40 | uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 41 | uses COREBOOT_EXTRA_VERSION |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 42 | uses _RAMBASE |
| 43 | uses CONFIG_GDB_STUB |
| 44 | uses CROSS_COMPILE |
| 45 | uses CC |
| 46 | uses HOSTCC |
| 47 | uses OBJCOPY |
| 48 | uses TTYS0_BAUD |
| 49 | uses TTYS0_BASE |
| 50 | uses TTYS0_LCS |
| 51 | uses DEFAULT_CONSOLE_LOGLEVEL |
| 52 | uses MAXIMUM_CONSOLE_LOGLEVEL |
| 53 | uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| 54 | uses CONFIG_CONSOLE_SERIAL8250 |
| 55 | uses HAVE_INIT_TIMER |
| 56 | uses CONFIG_GDB_STUB |
| 57 | uses CONFIG_CHIP_NAME |
| 58 | uses CONFIG_CONSOLE_VGA |
| 59 | uses CONFIG_PCI_ROM_RUN |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 60 | uses HW_MEM_HOLE_SIZEK |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 61 | uses K8_HT_FREQ_1G_SUPPORT |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 62 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 63 | uses USE_DCACHE_RAM |
| 64 | uses DCACHE_RAM_BASE |
| 65 | uses DCACHE_RAM_SIZE |
| 66 | uses CONFIG_USE_INIT |
| 67 | |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 68 | uses SERIAL_CPU_INIT |
| 69 | |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 70 | uses ENABLE_APIC_EXT_ID |
| 71 | uses APIC_ID_OFFSET |
| 72 | uses LIFT_BSP_APIC_ID |
| 73 | |
Yinghai Lu | 9a791df | 2006-04-03 20:38:34 +0000 | [diff] [blame] | 74 | uses HT_CHAIN_UNITID_BASE |
| 75 | uses HT_CHAIN_END_UNITID_BASE |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 76 | uses SB_HT_CHAIN_ON_BUS0 |
Yinghai Lu | 9a791df | 2006-04-03 20:38:34 +0000 | [diff] [blame] | 77 | uses SB_HT_CHAIN_UNITID_OFFSET_ONLY |
| 78 | |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 79 | uses CONFIG_LB_MEM_TOPK |
| 80 | |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 81 | ## ROM_SIZE is the size of boot ROM that this board will use. |
| 82 | #512K bytes |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 83 | default ROM_SIZE=524288 |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 84 | |
| 85 | #1M bytes |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 86 | #default ROM_SIZE=1048576 |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 87 | |
| 88 | ## |
| 89 | ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use |
| 90 | ## |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 91 | #default FALLBACK_SIZE=131072 |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 92 | #default FALLBACK_SIZE=0x40000 |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 93 | |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 94 | #FALLBACK: 256K-4K |
| 95 | default FALLBACK_SIZE=0x3f000 |
| 96 | #FAILOVER: 4K |
| 97 | default FAILOVER_SIZE=0x01000 |
| 98 | |
| 99 | #more 1M for pgtbl |
| 100 | default CONFIG_LB_MEM_TOPK=2048 |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 101 | |
| 102 | ## |
| 103 | ## Build code for the fallback boot |
| 104 | ## |
| 105 | default HAVE_FALLBACK_BOOT=1 |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 106 | default HAVE_FAILOVER_BOOT=1 |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 107 | |
| 108 | ## |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 109 | ## Build code to reset the motherboard from coreboot |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 110 | ## |
| 111 | default HAVE_HARD_RESET=1 |
| 112 | |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 113 | ## |
| 114 | ## Build code to export a programmable irq routing table |
| 115 | ## |
| 116 | default HAVE_PIRQ_TABLE=1 |
| 117 | default IRQ_SLOT_COUNT=11 |
| 118 | |
| 119 | ## |
| 120 | ## Build code to export an x86 MP table |
| 121 | ## Useful for specifying IRQ routing values |
| 122 | ## |
| 123 | default HAVE_MP_TABLE=1 |
| 124 | |
| 125 | ## |
| 126 | ## Build code to export a CMOS option table |
| 127 | ## |
| 128 | default HAVE_OPTION_TABLE=1 |
| 129 | |
| 130 | ## |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 131 | ## Move the default coreboot cmos range off of AMD RTC registers |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 132 | ## |
| 133 | default LB_CKS_RANGE_START=49 |
| 134 | default LB_CKS_RANGE_END=122 |
| 135 | default LB_CKS_LOC=123 |
| 136 | |
| 137 | ## |
| 138 | ## Build code for SMP support |
| 139 | ## Only worry about 2 micro processors |
| 140 | ## |
| 141 | default CONFIG_SMP=1 |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 142 | default CONFIG_MAX_CPUS=4 |
| 143 | default CONFIG_MAX_PHYSICAL_CPUS=2 |
| 144 | default CONFIG_LOGICAL_CPUS=1 |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 145 | |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 146 | default SERIAL_CPU_INIT=0 |
| 147 | |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 148 | #CHIP_NAME ? |
| 149 | #default CONFIG_CHIP_NAME=1 |
| 150 | |
arch import user (historical) | ef03afa | 2005-07-06 17:15:30 +0000 | [diff] [blame] | 151 | #1G memory hole |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 152 | default HW_MEM_HOLE_SIZEK=0x100000 |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 153 | |
Yinghai Lu | 9a791df | 2006-04-03 20:38:34 +0000 | [diff] [blame] | 154 | ##HT Unit ID offset, default is 1, the typical one |
| 155 | default HT_CHAIN_UNITID_BASE=0x0 |
| 156 | |
| 157 | ##real SB Unit ID, default is 0x20, mean dont touch it at last |
| 158 | #default HT_CHAIN_END_UNITID_BASE=0x0 |
| 159 | |
| 160 | #make the SB HT chain on bus 0, default is not (0) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 161 | default SB_HT_CHAIN_ON_BUS0=2 |
Yinghai Lu | 9a791df | 2006-04-03 20:38:34 +0000 | [diff] [blame] | 162 | |
| 163 | ##only offset for SB chain?, default is yes(1) |
| 164 | default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 |
| 165 | |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 166 | #Opteron K8 1G HT Support |
| 167 | default K8_HT_FREQ_1G_SUPPORT=1 |
| 168 | |
Myles Watson | a67c354c | 2008-09-18 15:30:42 +0000 | [diff] [blame^] | 169 | #VGA Console |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 170 | default CONFIG_CONSOLE_VGA=1 |
| 171 | default CONFIG_PCI_ROM_RUN=1 |
| 172 | |
| 173 | ## |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 174 | ## enable CACHE_AS_RAM specifics |
| 175 | ## |
Ronald G. Minnich | fb0a64b | 2005-11-23 21:01:08 +0000 | [diff] [blame] | 176 | default USE_DCACHE_RAM=1 |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 177 | default DCACHE_RAM_BASE=0xcf000 |
| 178 | default DCACHE_RAM_SIZE=0x1000 |
Yinghai Lu | 9a791df | 2006-04-03 20:38:34 +0000 | [diff] [blame] | 179 | default CONFIG_USE_INIT=0 |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 180 | |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 181 | default ENABLE_APIC_EXT_ID=0 |
Stefan Reinauer | 806e146 | 2005-12-01 10:54:44 +0000 | [diff] [blame] | 182 | default APIC_ID_OFFSET=0x10 |
| 183 | default LIFT_BSP_APIC_ID=0 |
| 184 | |
| 185 | |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 186 | ## |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 187 | ## Build code to setup a generic IOAPIC |
| 188 | ## |
| 189 | default CONFIG_IOAPIC=1 |
| 190 | |
| 191 | ## |
| 192 | ## Clean up the motherboard id strings |
| 193 | ## |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 194 | default MAINBOARD_PART_NUMBER="s2895" |
| 195 | default MAINBOARD_VENDOR="Tyan" |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 196 | default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 |
| 197 | default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895 |
| 198 | |
| 199 | ### |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 200 | ### coreboot layout values |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 201 | ### |
| 202 | |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 203 | ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 204 | default ROM_IMAGE_SIZE = 65536 |
| 205 | |
| 206 | ## |
| 207 | ## Use a small 8K stack |
| 208 | ## |
| 209 | default STACK_SIZE=0x2000 |
| 210 | |
| 211 | ## |
| 212 | ## Use a small 16K heap |
| 213 | ## |
| 214 | default HEAP_SIZE=0x4000 |
| 215 | |
| 216 | ## |
| 217 | ## Only use the option table in a normal image |
| 218 | ## |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 219 | default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 220 | |
| 221 | ## |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 222 | ## Coreboot C code runs at this location in RAM |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 223 | ## |
Yinghai Lu | 6d74d76 | 2006-10-04 23:57:49 +0000 | [diff] [blame] | 224 | default _RAMBASE=0x00100000 |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 225 | |
| 226 | ## |
| 227 | ## Load the payload from the ROM |
| 228 | ## |
Ed Swierk | be13dc7 | 2006-12-15 12:56:28 +0000 | [diff] [blame] | 229 | default CONFIG_ROM_PAYLOAD = 1 |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 230 | |
| 231 | ### |
| 232 | ### Defaults of options that you may want to override in the target config file |
| 233 | ### |
| 234 | |
| 235 | ## |
| 236 | ## The default compiler |
| 237 | ## |
Uwe Hermann | ff54db4 | 2007-02-02 17:08:04 +0000 | [diff] [blame] | 238 | default CC="$(CROSS_COMPILE)gcc -m32" |
| 239 | default HOSTCC="gcc" |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 240 | |
| 241 | ## |
| 242 | ## Disable the gdb stub by default |
| 243 | ## |
| 244 | default CONFIG_GDB_STUB=0 |
| 245 | |
| 246 | ## |
| 247 | ## The Serial Console |
| 248 | ## |
| 249 | |
| 250 | # To Enable the Serial Console |
| 251 | default CONFIG_CONSOLE_SERIAL8250=1 |
| 252 | |
| 253 | ## Select the serial console baud rate |
| 254 | default TTYS0_BAUD=115200 |
| 255 | #default TTYS0_BAUD=57600 |
| 256 | #default TTYS0_BAUD=38400 |
| 257 | #default TTYS0_BAUD=19200 |
| 258 | #default TTYS0_BAUD=9600 |
| 259 | #default TTYS0_BAUD=4800 |
| 260 | #default TTYS0_BAUD=2400 |
| 261 | #default TTYS0_BAUD=1200 |
| 262 | |
| 263 | # Select the serial console base port |
| 264 | default TTYS0_BASE=0x3f8 |
| 265 | |
| 266 | # Select the serial protocol |
| 267 | # This defaults to 8 data bits, 1 stop bit, and no parity |
| 268 | default TTYS0_LCS=0x3 |
| 269 | |
| 270 | ## |
Stefan Reinauer | f8ee180 | 2008-01-18 15:08:58 +0000 | [diff] [blame] | 271 | ### Select the coreboot loglevel |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 272 | ## |
| 273 | ## EMERG 1 system is unusable |
| 274 | ## ALERT 2 action must be taken immediately |
| 275 | ## CRIT 3 critical conditions |
| 276 | ## ERR 4 error conditions |
| 277 | ## WARNING 5 warning conditions |
| 278 | ## NOTICE 6 normal but significant condition |
| 279 | ## INFO 7 informational |
| 280 | ## DEBUG 8 debug-level messages |
| 281 | ## SPEW 9 Way too many details |
| 282 | |
| 283 | ## Request this level of debugging output |
arch import user (historical) | 6ca7636 | 2005-07-06 17:17:25 +0000 | [diff] [blame] | 284 | default DEFAULT_CONSOLE_LOGLEVEL=8 |
arch import user (historical) | 98d0d30 | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 285 | ## At a maximum only compile in this level of debugging |
| 286 | default MAXIMUM_CONSOLE_LOGLEVEL=8 |
| 287 | |
| 288 | ## |
| 289 | ## Select power on after power fail setting |
| 290 | default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" |
| 291 | |
| 292 | ### End Options.lb |
| 293 | end |