blob: 3d9ffb5415a8452fd5e279c57834d717ef927e22 [file] [log] [blame]
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -05001#include <console/console.h>
2#include <arch/smp/mpspec.h>
3#include <device/pci.h>
4#include <string.h>
5#include <stdint.h>
6#include <cpu/amd/amdk8_sysconf.h>
7
8extern unsigned char bus_ck804_0; //1
9extern unsigned char bus_ck804_1; //2
10extern unsigned char bus_ck804_2; //3
11extern unsigned char bus_ck804_3; //4
12extern unsigned char bus_ck804_4; //5
13extern unsigned char bus_ck804_5; //6
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050014extern unsigned apicid_ck804;
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050015
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050016
17static void *smp_write_config_table(void *v)
18{
19 struct mp_config_table *mc;
20 unsigned sbdn;
21 int i, bus_isa;
22
23 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
24
25 mptable_init(mc, LOCAL_APIC_ADDR);
26
27 smp_write_processors(mc);
28
29 get_bus_conf();
30 sbdn = sysconf.sbdn;
31
32 mptable_write_buses(mc, NULL, &bus_isa);
33
34/*I/O APICs: APIC ID Version State Address*/
35 {
36 device_t dev;
37 struct resource *res;
38 uint32_t dword;
39
40 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
41 if (dev) {
42 res = find_resource(dev, PCI_BASE_ADDRESS_1);
43 if (res) {
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080044 smp_write_ioapic(mc, apicid_ck804, 0x11,
45 res2mmio(res, 0, 0));
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050046 }
47
48 /* Initialize interrupt mapping*/
49
50 dword = 0x0120d218;
51 pci_write_config32(dev, 0x7c, dword);
52
53 dword = 0x12008a00;
54 pci_write_config32(dev, 0x80, dword);
55
56 dword = 0x0000007d;
57 pci_write_config32(dev, 0x84, dword);
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050058 }
59
60 }
61
62 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
63
64// Onboard ck804 smbus
65 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
66
67// Onboard ck804 USB 1.1
68 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
69
70// Onboard ck804 USB 2
71 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
72
73// Onboard ck804 SATA 0
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
75
76// Onboard ck804 SATA 1
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
78
79//Slot PCIE x16
Elyes HAOUASa5aad2e2016-09-19 09:47:16 -060080 for(i = 0; i < 4; i++) {
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00 << 2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050082 }
83
84//Slot PCIE x4
Elyes HAOUASa5aad2e2016-09-19 09:47:16 -060085 for(i = 0; i < 4; i++) {
86 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00 << 2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050087 }
88
Jonathan A. Kollasch553fe1c2013-10-15 16:45:51 -050089//Onboard SM720 VGA
Elyes HAOUASa5aad2e2016-09-19 09:47:16 -060090 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6 << 2)|0, apicid_ck804, 0x13); // 19
Jonathan A. Kollasche1ffd9e2013-10-15 14:26:34 -050091
92/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
93 mptable_lintsrc(mc, bus_isa);
94 /* There is no extension information... */
95
96 /* Compute the checksums */
97 return mptable_finalize(mc);
98}
99
100unsigned long write_smp_table(unsigned long addr)
101{
102 void *v;
103 v = smp_write_floating_table(addr, 0);
104 return (unsigned long)smp_write_config_table(v);
105}