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Uwe Hermann20a98c92009-06-05 23:02:43 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Uwe Hermann20a98c92009-06-05 23:02:43 +000015 */
16
Uwe Hermann20a98c92009-06-05 23:02:43 +000017#include <arch/pirq_routing.h>
Uwe Hermann20a98c92009-06-05 23:02:43 +000018
Stefan Reinauera47bd912012-11-15 15:15:15 -080019static const struct irq_routing_table intel_irq_routing_table = {
Uwe Hermann0ffff342009-06-07 13:46:50 +000020 PIRQ_SIGNATURE, /* u32 signature */
21 PIRQ_VERSION, /* u16 version */
Stefan Reinauer08670622009-06-30 15:17:49 +000022 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
Uwe Hermann0ffff342009-06-07 13:46:50 +000023 0x00, /* Where the interrupt router lies (bus) */
24 (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */
Uwe Hermann4e2ffb82009-07-15 00:03:28 +000025 0xca0, /* IRQs devoted exclusively to PCI usage */
Uwe Hermann0ffff342009-06-07 13:46:50 +000026 0x1106, /* Vendor */
Uwe Hermann4e2ffb82009-07-15 00:03:28 +000027 0x596, /* Device */
Uwe Hermann0ffff342009-06-07 13:46:50 +000028 0, /* Miniport */
29 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
Uwe Hermann4e2ffb82009-07-15 00:03:28 +000030 0xdb, /* Checksum. 0xa0? */
Uwe Hermann20a98c92009-06-05 23:02:43 +000031 {
Uwe Hermann0ffff342009-06-07 13:46:50 +000032 /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
Uwe Hermann4e2ffb82009-07-15 00:03:28 +000033 {0x00, (0x02 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x1, 0x0},
34 {0x00, (0x03 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x2, 0x0},
35 {0x00, (0x03 << 3) | 0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x3, 0x0},
36 {0x04, (0x04 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}}, 0x4, 0x0},
37 {0x04, (0x0e << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x5, 0x0},
38 {0x00, (0x11 << 3) | 0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
39 {0x00, (0x0f << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
40 {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
41 {0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
42 {0x00, (0x02 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0},
43 {0x00, (0x03 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0},
44 {0x00, (0x03 << 3) | 0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0},
45 {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
Uwe Hermann20a98c92009-06-05 23:02:43 +000046 }
47};
48
49inline unsigned long write_pirq_routing_table(unsigned long addr)
50{
Stefan Reinauera47bd912012-11-15 15:15:15 -080051 return copy_pirq_routing_table(addr, &intel_irq_routing_table);
Uwe Hermann20a98c92009-06-05 23:02:43 +000052}